Columnar Transistor Memory Cell for Low Power High Integration
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices using unipolar memory cells with diodes face challenges in power consumption and integration due to the need for all word lines to rise during access, leading to slow first access and high power consumption, while devices using transistors offer faster access and reduced power consumption but with poorer integration.
Innovation Solution
A nonvolatile semiconductor memory device is designed with a memory cell array comprising a variable resistor and a columnar transistor connected in series, allowing only the selected word line and bit line to be activated during access, reducing power consumption and enabling high integration by using a columnar transistor with the word line as its gate, and incorporating a diode-based memory cell for enhanced integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a unipolar memory cell with a diode is used, then integration is improved, but power consumption increases and first access speed decreases
Solution Approach 1:
The memory cell is segmented into two distinct functional components: a diode for rectification and integration, and a transistor for selective access and power control. This segmentation allows each component to optimize its specific function while working together to resolve the contradiction between integration and power consumption.
Solution Approach 2:
The diode acts as an intermediary element that enables high integration through its compact structure, while the transistor serves as a mediator that controls power consumption and access timing. The interaction between these two intermediaries resolves the technical contradiction by allowing the system to benefit from both high integration and low power consumption.
2Quantity of substance
If a unipolar memory cell with a diode is used, then integration is improved, but first access speed decreases
Solution Approach 1:
The memory cell is segmented into two distinct functional components: a diode for rectification and integration, and a transistor for selective access and power control. This segmentation allows each component to optimize its specific function while working together to resolve the contradiction between integration and power consumption.
Solution Approach 2:
The diode acts as an intermediary element that enables high integration through its compact structure, while the transistor serves as a mediator that controls power consumption and access timing. The interaction between these two intermediaries resolves the technical contradiction by allowing the system to benefit from both high integration and low power consumption.
3Use of energy by moving object
If a bipolar memory cell with a transistor is used, then power consumption is reduced and access speed is improved, but integration deteriorates
Solution Approach 1:
The invention merges the advantages of both diode-based and transistor-based memory cells by combining them into a single hybrid cell structure. The diode provides compactness for high integration, while the transistor provides selective access for low power consumption and high speed. This merging resolves the contradiction by allowing the system to achieve all three goals simultaneously.
Solution Approach 2:
The hybrid memory cell structure serves multiple functions: the diode provides rectification and compact integration, while the transistor provides selective access control and power management. This multi-functionality allows the single cell structure to resolve the technical contradiction between integration and power consumption/speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption, accelerates the first access, and achieves high integration while maintaining the benefits of bipolar memory cell operation, such as reduced power consumption and high throughput.
Implementation Method 1
a variable resistor, which is electrically rewritable, stores a resistance value as data in a nonvolatile manner
Implementation Method 2
the transistor being a columnar transistor having the second line arranged at its side face as a gate
Data Source
AI summary
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array layer including a first line; a plurality of second and third lines that are formed below or above the first line and cross each other; and a plurality of memory cells arranged at each intersection of the second and third lines, the memory cell including a variable resistor and a transistor, which are connected to each other in series between the first line and the third line, the variable resistor being electrically rewritable and storing a resistance value as data in a nonvolatile manner, and the transistor being a columnar transistor having the second line arranged at its side face as a gate.