Comb-Fishbone Interconnect Layout for Low-Resistance MOS Routing
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Solution Overview
Problem
Current integrated circuit (IC) layouts face challenges with increased parasitic via resistance and capacitance, particularly at smaller technology nodes, due to the use of grid-style metal interconnects which limit efficient transistor connections and lead to higher IR drop and electromigration issues.
Innovation Solution
The implementation of a non-grid style layout with comb/fishbone interconnect structures that reduce via resistance and parasitic capacitance by using unidirectional interconnect stacks and additional source-coupled interconnects, allowing for more parallelized vias and optimized metal layer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If grid-style metal interconnects are used, then layout simplicity is maintained, but via resistance and parasitic capacitance increase
Solution Approach 1:
The interconnect structure is segmented into vertical interconnect stacks and horizontal comb/fishbone interconnects, creating a non-grid layout that reduces via resistance by distributing current through multiple parallel paths rather than relying on a uniform grid pattern
Solution Approach 2:
The patent transitions from a two-dimensional grid layout to a three-dimensional interconnect structure with stacks extending vertically and comb/fishbone patterns extending horizontally, utilizing multiple layers to reduce parasitic effects and improve current distribution
2Loss of energy
If grid-style metal interconnects are used, then manufacturing process is simplified, but IR drop increases
Solution Approach 1:
The interconnect path is segmented into multiple parallel vertical stacks and horizontal comb/fishbone segments, distributing current flow to reduce IR drop while maintaining manufacturability through standardized fabrication processes
Solution Approach 2:
The patent applies different interconnect patterns (comb vs. fishbone) in different local regions of the circuit, optimizing current distribution and reducing IR drop in high-current areas while using simpler patterns in lower-current regions
3Object-generated harmful factors
If grid-style metal interconnects are used, then layout uniformity is maintained, but parasitic capacitance increases
Solution Approach 1:
The continuous grid interconnect is segmented into discrete vertical stacks and horizontal comb/fishbone elements, reducing parasitic capacitance by minimizing overlapping metal areas while maintaining electrical connectivity through controlled via structures
Solution Approach 2:
The patent extracts the essential connectivity function from the uniform grid pattern, retaining only the necessary interconnect paths in vertical and horizontal directions while removing redundant overlapping structures that contribute to parasitic capacitance
Data Source
AI summary
An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.