Comb-Shaped Gate Structure for Lateral DMOS Transistors
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Solution Overview
Problem
Lateral double-diffused metal-oxide-semiconductor (MOS) transistors require a balance between low on-resistance and high breakdown voltage, which existing designs struggle to achieve effectively, especially in high voltage integrated circuits.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with an epitaxial layer, isolation areas, body and drift areas, and a local oxidation of silicon (LOCOS) insulating layer, featuring a comb-shaped gate structure with alternating conductive and non-conductive areas and undoped conductive materials to minimize overlap capacitance and maintain high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used in lateral double-diffused MOS transistors, then the device can be manufactured with standard processes, but the on-resistance is high and breakdown voltage is limited
Solution Approach 1:
The gate structure is segmented into multiple fingers arranged in a comb pattern, with alternating conductive and non-conductive regions. This segmentation reduces the overlap area between the gate and drain, thereby reducing overlap capacitance and improving breakdown voltage while maintaining low on-resistance through parallel current paths
Solution Approach 2:
The gate structure implements local quality by having different conductive properties in different regions - the finger gate portions directly over the drift area use undoped conductive material with lower conductivity to reduce overlap capacitance, while maintaining appropriate conductivity in other regions for optimal device performance
2Loss of energy
If the gate area is increased to reduce on-resistance, then current flow improves, but overlap capacitance increases and breakdown voltage decreases
Solution Approach 1:
The gate is divided into multiple finger segments that extend into the drift area, creating a comb-like structure. This segmentation allows the gate to maintain a large effective area for low on-resistance while the alternating non-conductive regions reduce the actual overlap capacitance with the drain, thus improving breakdown voltage
Solution Approach 2:
The gate structure transitions from a conventional planar design to a three-dimensional comb structure with fingers extending in multiple directions. This dimensional change increases the effective gate area for current conduction while strategically positioning non-conductive regions to minimize capacitive overlap, simultaneously addressing both on-resistance and breakdown voltage requirements
3Loss of energy
If doped conductive material is used in the gate, then conductivity is high and on-resistance is low, but overlap capacitance increases
Solution Approach 1:
The gate structure applies local quality by using undoped conductive material specifically in the finger gate regions that overlap the drift area, where lower conductivity reduces overlap capacitance. Other regions of the gate maintain appropriate doping levels for optimal electrical connection and current conduction, achieving a balance between on-resistance and breakdown voltage
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a LOCOS insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the LOCOS insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the LOCOS insulating layer from a direction of the body area.


