Combination FinFET Channel with Dual Semiconductor Materials
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Solution Overview
Problem
Current FinFETs face challenges in achieving high drive currents with smaller dimensions due to limitations in semiconductor materials, particularly silicon, which restricts their mobility and effectiveness in next-generation electronic devices.
Innovation Solution
A combination FinFET structure is developed, where the channel region consists of two different semiconductor materials: a high mobility material like germanium or indium gallium arsenic, and a low interface trap density material like silicon, with a specific height ratio greater than 0.6, to balance mobility and trap density, enhancing overall electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional silicon material is used in FinFET channel region, then manufacturing process is simple and reliable, but mobility is limited and drive current is insufficient
Solution Approach 1:
The patent applies composite materials by forming a channel region with multiple semiconductor materials stacked vertically. A first semiconductor material (e.g., germanium, indium gallium arsenic) with high carrier mobility is combined with a second semiconductor material (e.g., silicon) with low interface trap density. The first material occupies the lower portion of the channel region while the second material occupies the upper portion, creating a composite structure that simultaneously achieves high mobility and low trap density, resolving the contradiction between speed and reliability.
2Productivity
If high mobility semiconductor materials are used, then drive current increases, but interface trap density increases
Solution Approach 1:
The patent applies local quality by assigning different materials to different vertical positions within the channel region. The first semiconductor material with high mobility is placed in the lower portion where it contributes to drive current, while the second semiconductor material with low interface trap density is placed in the upper portion near the gate interface where it reduces trap density. This spatial differentiation of material properties allows the device to simultaneously achieve high drive current and high reliability.
3Area of moving object
If FinFET dimensions are reduced for down-scaling, then integration density increases, but achieving high drive current becomes more difficult
Solution Approach 1:
The patent uses composite materials in the channel region to maintain high drive current in scaled-down FinFETs. By combining high-mobility materials (germanium, indium gallium arsenic) with low-trap-density materials (silicon) in a vertical stack, the invention achieves enhanced carrier transport properties that compensate for the reduced device dimensions, allowing high drive current to be maintained even as the device footprint is reduced for higher integration density.
Data Source
AI summary
An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.