Combinational Logic Gate Authentication Circuit Reduces Computational Power
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Solution Overview
Problem
Existing authentication methods require substantial computational power in claimants, which is cost-prohibitive for devices like simple mobile devices, as they need to perform advanced mathematical functions for challenge-response protocols.
Innovation Solution
The method utilizes combinational logic, such as AND and OR operations, to authenticate claimants, reducing the required computational power to only that needed for combinational logic gates, allowing for lower-cost electronics and secure authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetrical or asymmetrical cryptography is used for authentication, then security is improved, but computational power requirement increases
Solution Approach 1:
The patent extracts the complex cryptographic computations from the claimant device and relocates them to the verifier system. The claimant only needs to perform simple combinational logic operations (AND, OR gates), while the verifier handles the computationally intensive cryptographic functions, thus resolving the contradiction between security and computational power requirements.
Solution Approach 2:
The patent introduces a cryptographic hash function as an intermediary mechanism. Instead of requiring the claimant to perform complex cryptographic operations, the hash function transforms the challenge and secret into a response that can be verified by the verifier, which has the computational power to handle the cryptographic verification.
2Ease of operation
If microprocessor-like computational power is provided in the claimant, then authentication capability is improved, but device cost increases
Solution Approach 1:
The patent replaces expensive microprocessor-like computational components with inexpensive combinational logic gates (AND, OR gates) in the claimant device. These simple logic gates are much cheaper and can be implemented in very basic electronic devices, thus resolving the contradiction between authentication capability and device cost.
Solution Approach 2:
The patent substitutes complex sequential processing (microprocessor operations) with simple combinational logic operations. Instead of using a microprocessor that requires multiplication and modulation operations, the system uses basic logic gates that perform bitwise operations, dramatically reducing the computational hardware requirements and associated costs.
Data Source
AI summary
Methods for authenticating a property of an article in electrical communication with a verifier system including, for example, reading an identification code from the article, generating a challenge phrase from a verifier system, writing a challenge phrase to a first memory location on the article, reading a response phrase from the second memory location on the article, wherein the second memory location is configured to respond with a combinational logic gate output of the second memory location and the first memory location, generating a message authentication code by encrypting the identification code using a predetermined algorithm, generating a comparison code, wherein the comparison code is a combination logic gate output of the message authentication code and the challenge phrase, and determining if the comparison code is equivalent to the response phrase. Articles configured for use with the same.