Combinational Logic Circuit Optimization via Signature Matching
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Solution Overview
Problem
Optimizing hardware designs described in high-level hardware description languages (HDL) is a time-consuming process due to the need to try multiple optimization strategies for each synthesis, which slows down the synthesis process and requires significant computational resources.
Innovation Solution
A method that generates a signature for a circuit using unique integers assigned to inputs, combinational instances, and outputs, and uses an error correction function to match this signature with previously saved signatures, allowing for the selection of the optimal optimization strategy for the netlist, thereby reducing the need to test multiple strategies each time the design is synthesized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple optimization strategies are tried for each synthesis, then the optimal optimization strategy can be identified, but the synthesis process becomes significantly slower and requires more computational resources
Solution Approach 1:
The system performs preliminary actions by generating a signature for the combinational module and looking up the corresponding optimization strategy in a database before the actual synthesis process. This preliminary identification of the optimal strategy eliminates the need to test multiple strategies during synthesis, thereby maintaining optimization quality while significantly improving synthesis speed.
Solution Approach 2:
The patent creates a signature that copies the essential structural information of the combinational module into a compact form. This signature can be stored and reused, allowing the system to quickly identify the optimal optimization strategy without re-evaluating all possible strategies, thus resolving the contradiction between thorough optimization and synthesis speed.
2Reliability
If multiple optimization strategies are tested separately for each combinational module, then each module can be optimized individually, but the overall optimization process becomes time-consuming
Solution Approach 1:
The system segments the optimization process into two distinct phases: (1) generating a signature for the combinational module which captures its structural characteristics, and (2) looking up the corresponding optimization strategy in a pre-computed database. This segmentation allows individual module optimization to be maintained while dramatically reducing the time required, as the lookup operation is much faster than testing multiple strategies.
Solution Approach 2:
The optimization strategies and their corresponding signatures are pre-computed and stored in a database before the actual synthesis process. This preliminary preparation allows the system to quickly retrieve the optimal strategy during synthesis without time-consuming testing, thus reducing optimization time while maintaining individual module optimization quality.
Data Source
AI summary
Examples herein describe techniques for optimizing a hardware design for an integrated circuit. Instead of trying multiple optimization strategies each time design code is synthesized, the embodiments herein describe identifying the optimal or best optimization strategy for a particular combinational module in the design code only one time. Then, each time the design code is synthesized in the future, a synthesis tool recognizes the combinational module and selects the best optimization strategy. To do so, the synthesis tool generates a signature using the circuit structure represented by a netlist. The synthesis tool traverses the netlist and assigns unique integers to the primary inputs, the combination instances, and the primary outputs. These integers can then be fed into a signature generator which outputs a signature for the combinational module.