Detecting Combinational Loop Instability via Break Registers
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Solution Overview
Problem
Existing technologies face challenges in detecting and addressing functional instability in emulated electronic circuits due to combinational loops, which can lead to oscillatory behavior and unpredictable outputs.
Innovation Solution
A method and system that automatically detect strongly connected components (SCCs) in circuit designs, insert break registers to break these SCCs, and use a relaxation clock to detect value mismatches across break registers, thereby identifying instability events and reporting them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If loops are present in the circuit to enable feedback functionality, then the circuit can perform oscillatory behavior and signal generation, but the circuit exhibits functional instability and unpredictable outputs
Solution Approach 1:
The patent segments the circuit into strongly connected components (SCCs) and identifies specific loops that cause instability. By breaking down the circuit into manageable components and analyzing each SCC independently, the system can target specific unstable loops without affecting the overall feedback functionality of the circuit.
Solution Approach 2:
The patent introduces break registers as intermediary elements inserted into unstable loops. These break registers act as mediators that capture and hold values, preventing the direct feedback path that causes oscillation while still allowing the loop structure to exist for functional purposes when needed.
2Difficulty of detecting and measuring
If break registers are inserted to break SCCs and detect instability, then instability detection capability is improved, but the device complexity increases
Solution Approach 1:
The break registers are configured to automatically detect and report instability conditions without requiring external monitoring equipment. The relaxation clock mechanism and value comparison logic are self-contained within the break register structure, allowing the circuit to self-diagnose instability issues.
Solution Approach 2:
The patent changes the operational parameters of the break registers by using a relaxation clock with a different frequency than the main system clock. This parameter change allows the break registers to sample and detect instability conditions that would be invisible at the original clock frequency, improving detection capability.
3Measurement precision
If a relaxation clock is used to clock break registers for instability detection, then detection accuracy is improved, but the loss of time increases due to additional clock cycles
Solution Approach 1:
The patent uses periodic relaxation clock cycles interspersed between main system clock cycles to detect instability. The relaxation clock operates periodically at specific intervals, allowing the break registers to sample the circuit state at critical moments without continuously interfering with the normal operation timing.
Solution Approach 2:
The relaxation clock mechanism applies a form of partial action by only clocking the break registers during specific relaxation cycles rather than continuously clocking all circuit elements. This selective timing provides sufficient detection accuracy while minimizing the overall time penalty.
Data Source
AI summary
A method includes: loading a circuit design including a plurality of combinational elements and controlled by a user clock; detecting strongly connected components (SCCs) corresponding to the plurality of combinational elements in the circuit design; inserting a plurality of break registers into the circuit design, each break register being between two combinational elements of a corresponding SCC of the SCCs to break the corresponding SCC, the plurality of break registers being clocked by a relaxation clock; detecting, by a processor, during an emulation run of the circuit design, one or more value mismatches across an input pin and an output pin of one or more break registers of the plurality of break registers based on a relaxation cycle of the relaxation clock, the one or more break registers being associated with one or more SCCs exhibiting instability; and reporting an instability event based on the one or more value mismatches.