Combinational Loop Handling in Formal Verification
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Solution Overview
Problem
Current methods for handling combinational loops in electronic design verification are inefficient, often leading to false positives and negatives, and are impractical due to complexity and the need for manual inspection, especially when dealing with large-scale electronic designs.
Innovation Solution
A computer-implemented method that identifies and models combinational loops, extracts logic conditions, and provides a graphical user interface to rank and display constraint candidates, determining conflicts and disabling loops to prevent false results, thereby simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the dual-rail model is used to analyze combinational loops, then the analysis can determine whether loops are functional or structural, but the complexity and state-space explosion prevent convergence and useful results
Solution Approach 1:
The patent segments the combinational loop analysis into multiple independent proof runs, each handling a single loop. This divides the complex state space into manageable portions that can be analyzed separately, avoiding state-space explosion while maintaining analysis accuracy.
Solution Approach 2:
The patent performs preliminary actions by automatically breaking loops at identified cutpoints before formal verification. This preprocessing step converts functional loops into structural ones, enabling standard verification techniques to proceed without encountering the complexity of functional loop analysis.
2Ease of operation
If manual inspection is used to identify and break combinational loops, then verification can proceed, but the process is difficult, error-prone and impracticable for large-scale designs
Solution Approach 1:
The system performs self-service by automatically identifying combinational loops, determining their functional nature, selecting appropriate cutpoints, and breaking them without human intervention. This automation eliminates manual errors while maintaining reliability through systematic algorithms.
Solution Approach 2:
The patent changes the state of loop handling by transitioning from manual inspection parameters to automated analysis parameters. The system modifies loop characteristics through automatic cutpoint insertion, transforming the verification process into a reliable, scalable operation suitable for large-scale designs.
3Measurement precision
If loop cutpoints are constrained to be equal to prevent false positives, then verification accuracy improves, but false negatives may occur and results may be inconsistent across different formal proof runs
Solution Approach 1:
The patent introduces dynamics by adaptively selecting cutpoints based on loop characteristics and verification context. The system dynamically adjusts the breaking strategy for each loop, choosing optimal cutpoints that maintain accuracy while avoiding false negatives and ensuring consistency across proof runs.
4Reliability
If serial analysis of loops is performed to avoid false classifications, then accuracy is maintained, but the bottleneck prevents efficient processing of designs with multiple loops
Solution Approach 1:
The patent segments the loop analysis task into independent units that can be processed in parallel. Each loop is analyzed separately with its own proof run, but the segmentation enables concurrent execution across multiple loops, eliminating the serial bottleneck while maintaining accurate classification through individualized analysis.
Data Source
AI summary
The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.