Combinational Loop Emulation With Selective Extra Clock Cycles

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Solution Overview

Problem

Conventional processor-based emulation systems for IC layouts with combinational loops face instability and inefficiency due to the need for loop breakers, which require additional clock cycles, leading to erratic behavior and prolonged compile times in complex designs.

Innovation Solution

EDA software systems intelligently manage loop breakers by analyzing the consumer type of loop break elements to selectively apply extra clock cycles based on the change in state and consumer type, avoiding unnecessary frequency increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If loop breakers are inserted in combinational loop paths to enable emulation, then the system can operate clocked devices, but the system clock becomes unstable and unpredictable due to additional clock cycles required

Engineering Contradiction:
Improvesystem clock stabilityVSAvoidloop breaker management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts clock cycle application based on detected state changes in loop break elements. Instead of applying extra clock cycles unconditionally, the system monitors consumer types and state changes, applying clock cycles only when necessary. This dynamic approach stabilizes the system clock by eliminating unnecessary frequency variations while maintaining reliable operation of clocked devices.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback mechanisms by detecting state changes between consecutive clock cycles in loop break elements. This feedback information is used to intelligently determine whether additional clock cycles are needed, creating a closed-loop control system that responds to actual circuit conditions rather than applying fixed clocking strategies.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If extra clock cycles are applied to loop break elements to ensure correct value propagation, then accurate emulation is achieved, but compile times are prolonged in complex designs

Engineering Contradiction:
Improveemulation accuracyVSAvoidcompile time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system applies extra clock cycles partially rather than universally. Instead of applying additional clock cycles to all loop break elements unconditionally, the system selectively applies them only to elements where state changes are detected. This partial action approach maintains emulation accuracy for critical paths while avoiding unnecessary time consumption in paths that do not require additional clocking.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system changes the clocking parameter dynamically based on circuit state. When state changes are detected in loop break elements, the system adjusts the clock cycle application parameter to apply extra cycles; when no changes are detected, the parameter returns to normal operation. This parameter change strategy ensures accuracy when needed while minimizing compile time during normal operation.

Inventive Principle:
Principle #35Parameter changes

3Speed

If clock frequency is increased for loop break elements to propagate values within the same cycle, then emulation speed is improved, but system stability deteriorates due to erratic behavior

Engineering Contradiction:
Improvevalue propagation speedVSAvoidsystem clock stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The system uses periodic detection of state changes in loop break elements to determine when accelerated clocking is needed. Instead of continuously running at high frequency, the system operates at normal speed and periodically checks for state changes. When changes are detected, extra clock cycles are applied; otherwise, normal operation continues. This periodic action maintains stability while enabling speed improvement when necessary.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12536364B1Fanout-based combinational loop emulation
Publication Date: 2026.01.27 CADENCE DESIGN SYST INC
  • US12536364B1 patent drawing
  • US12536364B1 patent drawing
  • US12536364B1 patent drawing

AI summary

Methods and systems are provided for performing combinational loop emulation. The methods and systems access a circuit design comprising a loop break element in a combinational loop path, where the loop break element comprises an input and an output. The methods and systems detect a change between the input of the loop break element and the output of the loop break element. The methods and systems identify a type of consumer of the output of the loop break element in the combinational loop path. The methods and systems determine whether to apply an extra clock cycle to the loop break element based on the type of consumer of the output of the loop break element and the detected change between the input and the output of the loop break element.