Combinatorial Processing Test Chip for Semiconductor Screening
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Solution Overview
Problem
Traditional semiconductor processing methods are inefficient and costly due to the need for full wafer uniform processing, which slows down material development and increases costs, as they require multiple processing conditions and lengthy qualification times for new materials, and pose risks to fabrication plants.
Innovation Solution
A high-throughput combinatorial processing method using a test chip with multiple site-isolated regions allows for immediate testing of varied materials and processes, eliminating the need for lithography and etching steps, and enabling efficient screening of multiple materials and process sequences on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional full wafer uniform processing is used, then manufacturing consistency is maintained, but productivity decreases and development cycle time increases
Solution Approach 1:
The substrate is divided into multiple site-isolated regions, each capable of undergoing different processing conditions simultaneously. This segmentation allows parallel processing of multiple materials and process sequences on a single substrate, dramatically increasing throughput and reducing development cycle time while maintaining manufacturing consistency within each region.
Solution Approach 2:
Different regions of the substrate are assigned different material compositions and processing conditions tailored to specific testing needs. Each region maintains its own optimized processing parameters while the overall substrate provides a unified platform, enabling simultaneous evaluation of multiple process variations without compromising local quality control.
2Productivity
If traditional lithography and etching are used for each material tested, then device definition precision is achieved, but processing complexity increases and tool qualification time extends
Solution Approach 1:
Materials are deposited onto the substrate before any patterning or etching steps. The site-isolated regions are pre-defined through deposition masks or self-alignment techniques, allowing subsequent processing to be simplified. This preliminary material placement eliminates the need for separate lithography and etching sequences for each material, reducing processing complexity while maintaining high screening throughput.
Solution Approach 2:
The patent extracts and eliminates the traditional lithography and etching steps from the processing sequence for combinatorial screening. By using alternative methods such as direct deposition patterning or self-aligned processes, the complex multi-step lithography-etch cycles are removed, significantly reducing processing complexity and tool qualification requirements while maintaining device definition precision.
3Reliability
If new materials are tested using conventional processes, then material properties can be evaluated, but tool poisoning risk increases and chemical waste management becomes more difficult
Solution Approach 1:
The substrate is segmented into site-isolated regions that physically separate different material testing zones. This spatial segmentation prevents cross-contamination between new materials and existing process tools, eliminating tool poisoning risks. Each region can be processed independently with its own chemical environment, and waste chemicals are contained within specific regions, simplifying waste management while maintaining measurement accuracy.
Solution Approach 2:
The site-isolated region structure acts as an intermediary barrier between new materials and the broader fabrication environment. This intermediate structure allows new materials to be tested without direct exposure to shared tooling and process lines, preventing tool poisoning. The isolation regions also serve as containment structures for chemical waste, making it easier to manage and dispose of hazardous materials while preserving measurement reliability.
Data Source
AI summary
In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.