Combined Active Region Standard Cells for FinFET Layout Efficiency
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Solution Overview
Problem
The manufacturing of miniaturized semiconductor devices faces challenges such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage due to increased complexity, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
The introduction of second-type standard cells with enlarged active regions formed by joining adjacent active regions of first-type standard cells, utilizing interconnection wiring to enhance performance and reduce complexity, combined with FinFET devices that incorporate additional active fin structures to improve speed and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If standard semiconductor manufacturing processes are used for miniaturized devices, then geometric size decreases, but manufacturing complexity increases causing high yield loss and reduced reliability
Solution Approach 1:
The manufacturing process is divided into multiple pitch-based stages (first pitch, second pitch, third pitch) where each stage forms specific features independently. This segmentation allows complex 3D FinFET structures to be built through sequential, manageable steps rather than attempting to create the entire structure in one complex process, thereby reducing manufacturing complexity while achieving miniaturization.
Solution Approach 2:
The patent transitions from planar 2D transistor structures to 3D FinFET structures by adding vertical dimension through fin formation. The method creates fins extending upward from the substrate, enabling increased device density and performance without proportionally increasing manufacturing complexity, as the vertical structures are formed through standardized deposition and etching processes repeated across multiple pitches.
2Area of moving object
If active region area is increased to improve performance, then device speed and power improve, but manufacturing complexity and interconnection wiring increase
Solution Approach 1:
Multiple active regions from different standard cells are merged into a single continuous active region through the multi-pitch manufacturing process. This combining approach increases the total active region area for enhanced device performance while eliminating the need for separate interconnection wiring that would be required to connect discrete active regions, thereby reducing manufacturing complexity and wiring overhead.
Data Source
AI summary
A semiconductor device includes: a first power rail and a second power rail; a third power rail between the first and second power rails; a first cell arranged between the first power rail and the second power rail, wherein a cell height of the first cell is equal to a pitch between the first power rail and the second power rail; a second cell arranged between the first power rail and the third power rail, wherein a cell height of the second cell is equal to a pitch between the first power rail and the third power rail; an active fin structure arranged in the first cell; and a dummy fin structure aligned with the active fin structure. A first active region of the first cell includes a first width greater than a second width of a second active region in the second cell.