Combined Adder Pre-Adder High-Radix Multiplier Circuit
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Solution Overview
Problem
Circuits performing mathematical operations, such as those in symmetrical finite impulse response (FIR) filters, require multiple adder circuits, which are inefficient and consume significant integrated circuit device area, especially in programmable logic devices like FPGAs, and increasing the radix of multipliers introduces the need for non-power-of-two manipulations and additional adders.
Innovation Solution
A compressor followed by adders is used to simplify the initial adder of an adder-multiplier-adder structure, allowing for the combination of adjacent adders into a single adder, with a preprocessing stage that programmably zeros the first input value and a compressor circuit that processes bit positions using exclusive-OR gates and shared inputs to reduce device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple adder circuits are used in the adder-multiplier-adder structure, then the arithmetic operations can be performed, but the integrated circuit device area increases substantially
Solution Approach 1:
The patent combines adjacent adder circuits into a single adder by providing a compressor that outputs signals to both adders, allowing the adders to share common inputs and reduce overall circuit area while maintaining arithmetic operation capability
Solution Approach 2:
The compressor circuit serves multiple functions by processing bit positions and generating compressed output signals that can be input to multiple adders, enabling the same circuit structure to support various arithmetic operations without requiring separate dedicated circuits for each function
2Productivity
If the radix of the multiplier is increased to reduce compressor tree size, then the multiplication efficiency improves, but non-power-of-two manipulations are required which introduce the need for additional adders
Solution Approach 1:
The patent changes the operational parameters of the adder circuits by providing a compressor that can handle non-power-of-two radix values, allowing the adders to operate with modified input relationships that accommodate higher radix multiplication without requiring additional adder circuits
Data Source
AI summary
Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.