Combined Branch Predictor Using HighBits Registers

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Solution Overview

Problem

Modern processors face challenges in predicting branch targets, particularly for indirect branches, which can lead to instruction execution stalls due to the complexity of computing target addresses, and existing architectures often require increased storage and hardware resources to accommodate longer target addresses.

Innovation Solution

A branch predictor circuit that combines tagged conditional and indirect branch target predictions, using a combined predictor table with prediction logic to generate a predicted complete target address before execution, and employs HighBits registers to store infrequently changing upper address bits, reducing storage requirements and hardware costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the branch predictor stores complete target addresses for indirect branches, then prediction accuracy is improved, but storage requirements and hardware resources increase

Engineering Contradiction:

Improvebranch prediction accuracyVSAvoidstorage requirements

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the target address into two parts: a predicted partial target address stored in the predictor table and actual upper address bits stored in separate HighBits registers. This segmentation allows the predictor to store only the variable lower bits while capturing the stable upper bits externally, reducing storage requirements while maintaining prediction accuracy for complete target addresses.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the upper address bits from the complete target address storage requirement and places them in separate HighBits registers. This extraction removes the bulk of the storage burden from the predictor table, as only the variable lower bits need to be stored in the table, while the stable upper bits are maintained in registers that don't require predictor table entries.

Inventive Principle:

Principle #2Taking out (Extraction)

2Measurement precision

If the processor computes the complete target address before execution, then branch prediction accuracy is improved, but instruction execution stalls occur

Engineering Contradiction:

Improvebranch prediction accuracyVSAvoidinstruction execution stall

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary action by generating a predicted complete target address before the indirect branch instruction executes. The prediction logic combines the predicted partial target address from the table with the actual upper address bits from HighBits registers to produce the predicted complete target address in advance, allowing the processor to advance execution without waiting for the full address computation during instruction execution.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If the predictor table stores separate conditional and indirect branch predictions, then prediction accuracy is improved, but device complexity increases

Engineering Contradiction:

Improveprediction accuracyVSAvoidpredictor table structure

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the storage of conditional branch predictions and indirect branch predictions into a single combined predictor table. Each table entry can store either a conditional branch prediction or an indirect branch prediction, with the entry type indicated by a prediction type bit. This merging reduces device complexity by eliminating the need for separate predictor tables while maintaining the ability to accurately predict both branch types.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the predictor table universal by allowing each entry to serve dual purposes: storing either conditional branch predictions or indirect branch predictions based on the prediction type bit. This multi-functionality allows a single table structure to handle both prediction types, reducing overall device complexity while maintaining specialized prediction capabilities for each branch type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10776119B2Combined conditional branch and indirect branch target predictor

Publication Date: 2020.09.15 MARVELL ASIA PTE LTD

AI summary

An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.