Combined Coherence Point and Memory Cache Controller Unit Fabric Hops
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Solution Overview
Problem
In computing systems, particularly in multiprocessor ICs, cache coherence issues lead to stale data and inconsistent memory updates, increasing power consumption and latency due to the complexity of maintaining coherence across multiple agents accessing shared memory regions.
Innovation Solution
A computing system with a communication fabric, transaction processing queues, and memory pipelines, where each pipeline includes an arbiter, a combined coherence point, and a memory cache controller, reducing the number of command hops by processing transactions through a consolidated memory fabric, thereby minimizing power consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple separate units (coherence point and memory cache controller) are used to process memory transactions, then cache coherence and memory management functions are clearly separated, but the number of hops in the communication fabric increases and power consumption increases
Solution Approach 1:
The patent combines the coherence point and memory cache controller into a single integrated unit called a combined coherence point and memory cache controller (CCMCC). This merger eliminates the need for separate communication hops between these two functional units, reducing power consumption while maintaining all necessary cache coherence and memory management capabilities through unified processing within the single unit.
Solution Approach 2:
The combined coherence point and memory cache controller performs multiple functions simultaneously - it handles cache coherence operations, memory cache lookups, and memory control functions all within a single unit. This multi-functional approach consolidates what were previously separate specialized units, reducing fabric hops while preserving all required functionalities.
2Adaptability or versatility
If transactions are moved through multiple hops in the fabric to reach different processing units, then specialized processing can be performed at each unit, but latency increases and power consumption increases
Solution Approach 1:
By merging the coherence point and memory cache controller into a single unit, the patent eliminates intermediate transmission hops that caused latency. The unified unit can process coherence operations and memory cache lookups in sequence or parallel without the time penalty of fabric transmission delays between separate units.
Solution Approach 2:
The combined unit acts as an intermediary that consolidates multiple processing functions that previously required separate fabric hops. By performing coherence and cache operations within the same unit that receives the transaction, the patent eliminates the need for intermediate fabric transmission steps.
3Ease of manufacture
If separate coherence points and memory cache controllers are used, then each unit can be optimized for its specific function, but the overall system requires more fabric resources and has higher power consumption
Solution Approach 1:
The patent integrates multiple functional units into a single combined coherence point and memory cache controller, reducing the total number of units in the system. This consolidation maintains functional capabilities while simplifying the overall system architecture and reducing fabric resource requirements.
Data Source
AI summary
Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.