Combined Binary and Non-Binary Decoder Circuit for Low Error Floors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data processing systems face challenges with error floors when using high rate low density parity check codes due to short cycles, which degrade the performance of belief propagation decoder circuits, while maximum likelihood decoders are too complex for practical implementation.
Innovation Solution
The implementation of a combination data decoder circuit that includes both non-binary and binary data decoder circuits, which can operate in parallel and share common circuitry, allowing for the application of non-binary and binary data decode algorithms to yield decoded outputs that can be selectively used for subsequent operations, thereby addressing the limitations of existing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a belief propagation based decoder circuit is used with high rate low density parity check codes, then the decoding speed is improved, but the error floor becomes more severe due to short cycles
Solution Approach 1:
The decoder is segmented into multiple specialized components: a belief propagation decoder for fast initial decoding, a minimum sum decoder for handling short cycle errors, and a maximum likelihood decoder for final error correction. Each segment handles specific aspects of the decoding process, allowing the system to achieve both high speed and low error floor by distributing different functions across specialized decoder segments rather than relying on a single decoder type
Solution Approach 2:
The system dynamically changes decoding parameters by switching between different decoding algorithms based on the detected error patterns. When short cycles are detected causing error floor issues, the system transitions from belief propagation to minimum sum or maximum likelihood decoding, changing the fundamental parameters of the decoding process to adapt to the specific error conditions and maintain both speed and reliability
2Reliability
If a maximum likelihood decoder is used, then the decoding accuracy is improved, but the device complexity becomes too high for practical implementation
Solution Approach 1:
Instead of always applying the full complexity of maximum likelihood decoding, the system applies it partially or selectively only when needed based on error detection. The belief propagation decoder handles the majority of cases with lower complexity, while maximum likelihood decoding is activated only for specific error conditions, achieving high accuracy without the constant overhead of full maximum likelihood decoder complexity
Solution Approach 2:
The decoder architecture is segmented into hierarchical levels: belief propagation for routine decoding, minimum sum for intermediate error correction, and maximum likelihood for difficult cases. This segmentation allows the system to achieve maximum likelihood accuracy when needed while maintaining practical complexity by using simpler decoders for the majority of operations
3Reliability
If non-binary data decode algorithm is applied, then the decoding performance is improved, but the device complexity increases compared to binary decoding
Solution Approach 1:
The decoder circuit is designed with universal components that can function in both binary and non-binary modes. The same hardware infrastructure supports multiple decoding algorithms and data types, allowing the system to achieve improved non-binary decoding performance without proportionally increasing complexity, as the underlying circuitry serves multiple purposes across different operating modes
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.