Combined Error Correction Code for Memory Command Integrity

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Solution Overview

Problem

Current memory systems, such as DRAM, face challenges in efficiently detecting and correcting multiple errors in commands and inversion information due to limited error control codes, and in optimizing channel usage during direct link error correction modes, which affects data integrity and system efficiency.

Innovation Solution

The implementation of a combined error correction code generated by the host system for both commands and inversion information, allowing the memory device to perform error correction procedures using a larger number of bits, and the use of a single channel for transferring error control codes during direct link error correction modes to improve channel usage efficiency and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a single channel is used for transferring error control codes during direct link error correction modes, then channel usage efficiency is improved and power consumption is reduced, but the ability to transfer multiple types of control information simultaneously is limited

Engineering Contradiction:
Improvepower consumptionVSAvoidchannel functionality
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent combines the transfer of error control codes for both commands and inversion information onto a single channel during direct link error correction modes. This merging of functions onto one channel reduces the number of active signal paths, thereby lowering power consumption and improving channel usage efficiency while maintaining the ability to perform error correction operations.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If a combined error correction code is generated for both commands and inversion information, then error detection and correction capability is improved, but the complexity of error control procedures increases

Engineering Contradiction:
Improvedata integrityVSAvoiderror control procedure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent generates a combined error correction code that protects both commands and inversion information with a single code structure. This unified approach enhances reliability by providing comprehensive error protection across multiple data types while the systematic combination method keeps the complexity manageable through standardized processing procedures.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The combined error correction code serves multiple functions: it corrects errors in commands, corrects errors in inversion information, and maintains data integrity across the entire communication protocol. This multi-functional design improves reliability without requiring separate specialized error control mechanisms for each data type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If multiple channels are used for transferring error control codes, then the ability to transfer control information is improved, but channel usage efficiency decreases and power consumption increases

Engineering Contradiction:
Improvechannel usage efficiencyVSAvoidnumber of channels
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the transfer of multiple error control codes onto a single channel, consolidating what would traditionally require multiple separate communication paths into one unified channel. This reduces the quantity of active channels from multiple to one, thereby improving channel usage efficiency and reducing the overhead associated with managing multiple channels.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11748191B2Techniques for error correction at a memory device
Publication Date: 2023.09.05 MICRON TECHNOLOGY INC
  • US11748191B2 patent drawing
  • US11748191B2 patent drawing
  • US11748191B2 patent drawing

AI summary

Methods, systems, and devices for techniques for error correction at a memory device are described. In some examples, as part of transmitting a command to access data stored at a memory device, a host device may transmit a combined error control code to the memory device that may be generated using the command and associated inversion information. The memory device may use the received combined error control code to perform an error control procedure on both the command and the inversion information. In some examples, while in a direct link error control code procedure mode, the host system may transmit a command to access data stored at the memory device. The host system may use a same pin or channel to transmit both an error control code for the command and an error control code for the associated data.