Combined Gate Trench and Contact Etch Process for Power Semiconductors
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Solution Overview
Problem
Conventional fabrication processes for trench type power semiconductor devices involve multiple masks, leading to difficulties in forming complex structures and introducing defects due to alignment errors, resulting in variations in electrical performance such as on-state resistance (RDSon) and breakdown voltage.
Innovation Solution
A combined gate trench and contact etch process using a single patterned masking layer to form both gate and contact trenches in a one-shot trench process, ensuring precise alignment and eliminating misalignments, followed by subsequent steps to form conductive fillers and dopant regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple masks are used to etch gate and contact trenches separately, then complex structures can be formed, but alignment errors and defects are introduced
Solution Approach 1:
The patent combines the formation of gate trenches and contact trenches into a single etching step using one patterned masking layer, eliminating the need for separate masking and etching steps for each trench type. This merging approach maintains the ability to form complex structures while removing alignment errors between multiple masks, directly resolving the technical contradiction.
2Adaptability or versatility
If multiple masks are used for separate etching steps, then different trench dimensions can be achieved, but process difficulty and defects increase
Solution Approach 1:
The patent merges the formation of gate trenches and contact trenches into a single etching step using one patterned masking layer, eliminating the need for separate masking and etching steps for each trench type. This merging approach maintains the ability to form complex structures while removing alignment errors between multiple masks, directly resolving the technical contradiction.
3Productivity
If conventional multi-mask processes are used, then device fabrication can proceed, but variations in electrical performance occur
Solution Approach 1:
The patent combines the formation of gate trenches and contact trenches into a single etching step using one patterned masking layer, eliminating the need for separate masking and etching steps for each trench type. This merging approach maintains the ability to form complex structures while removing alignment errors between multiple masks, directly resolving the technical contradiction.
Data Source
AI summary
A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.