Combined Memory Block with Stacked Variable Resistance Cells
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Solution Overview
Problem
The complexity and cost of manufacturing data processing systems increase due to the integration of chips with different driving conditions, which complicates the integration of various function blocks on a single chip in semiconductor memory devices, particularly in SOC systems, where separate driving circuits are needed for different memory types.
Innovation Solution
A combined memory block is introduced, comprising a first memory unit for address mapping and data storage, and an additional memory unit forming a stacked structure, utilizing multi-level cells with variable resistance to enhance data storage efficiency and reduce power consumption, while allowing easier random access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate driving circuits are used for different memory types in SOC systems, then different memory types can be integrated, but the manufacturing process becomes complicated and costly
Solution Approach 1:
The patent combines multiple memory types (first memory unit and second memory unit with stacked structure) into a single integrated memory block that shares common driving circuits. This merging approach allows different memory types to be integrated while eliminating the need for separate driving circuits for each memory type, thereby reducing manufacturing process complexity and cost.
Solution Approach 2:
The integrated memory block is designed with universal driving circuits that can control and drive both the first memory unit and the second memory unit with stacked structure. This multi-functionality allows a single set of driving circuits to serve multiple memory types, simplifying the manufacturing process while maintaining the ability to integrate different memory types in the SOC system.
2Quantity of substance
If flash memory devices use a stack structure of two gates, then integration density increases, but operation voltage becomes high requiring separate boosting circuits
Solution Approach 1:
The patent combines the first memory unit and the second memory unit with stacked structure into an integrated memory block that shares common driving circuits. This merging approach allows different memory types to be integrated while eliminating the need for separate driving circuits for each memory type, thereby reducing manufacturing process complexity and cost.
Solution Approach 2:
The integrated memory block is designed with universal driving circuits that can control and drive both the first memory unit and the second memory unit with stacked structure. This multi-functionality allows a single set of driving circuits to serve multiple memory types, simplifying the manufacturing process while maintaining the ability to integrate different memory types in the SOC system.
3Speed
If DRAM devices are used for high speed operation, then random data access is easier, but periodic refresh is required due to volatile property
Solution Approach 1:
The patent segments the memory system into two distinct memory units: the first memory unit optimized for high-speed operation with easy random data access, and the second memory unit with stacked structure providing non-volatile data retention. This segmentation allows each memory unit to fulfill its specific function without compromising the other, achieving both high speed operation and data retention.
Solution Approach 2:
The patent implements a nested structure where the second memory unit with stacked structure is integrated within the same memory block as the first memory unit. This nesting allows the non-volatile memory to provide data retention support while the volatile memory handles high-speed operations, creating a hierarchical memory system within a compact integrated block.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the manufacturing process and reduces costs by enabling high-speed data processing with low power consumption and efficient data storage, integrating different memory types into a single system with improved operational speed and reduced area occupancy.
Implementation Method 1
the memory unit and the storage unit together form multi-level cells having variable resistance in storing data
Data Source
AI summary
A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.