Combined Memory Selector Device With Electron Barrier
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Solution Overview
Problem
Modern electronic neural networks face challenges in efficiently representing biological neurons and synapses due to high leakage current and power consumption, particularly in devices with discrete barrier layers and separate active layers, which hinder their performance in complex tasks and low-power applications.
Innovation Solution
The development of a combined memory and selector device with a self-rectifying structure, utilizing a combination of amorphous silicon, silicon dioxide, and titanium oxide layers, where the thickness ratios and doping of the active layer are optimized to reduce leakage current and power consumption, and a work function differential is introduced between electrodes to enhance selectivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discrete barrier layer and separate active layer are used in memory devices, then device functionality is achieved, but leakage current increases and power consumption rises
Solution Approach 1:
The patent combines the barrier layer and active layer into a unified structure where the barrier layer is positioned between the electrode and active layer, creating an integrated memory device that reduces interface defects and improves overall device performance while maintaining functionality and reducing leakage current
Solution Approach 2:
The patent employs composite material structures with specific layer compositions including barrier layers made of materials such as aluminum oxide, silicon oxide, or titanium oxide, combined with active layers of transition metal oxides, creating a composite structure that optimizes both electrical performance and energy efficiency
2Adaptability or versatility
If conventional memory and selector devices are used in neural networks, then basic computation is possible, but power consumption is high
Solution Approach 1:
The patent designs memory devices that can function both as memory elements and as synaptic weights in neural networks, enabling multi-functional operation where the same device structure supports both data storage and computation, thereby reducing overall system power consumption
Solution Approach 2:
The patent optimizes electrical parameters such as operating voltage, resistance states, and switching characteristics of the memory device to enable efficient neural network computation at lower power levels, allowing the device to adapt its electrical parameters for different computational tasks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces leakage current and power requirements, allowing for efficient operation at lower voltages, thereby improving the performance and power efficiency of neural network devices.
Implementation Method 1
a bottom electrode, a tunneling layer on the bottom electrode, an active layer on the tunneling layer
Implementation Method 2
a barrier layer on the first electrode, wherein the barrier layer comprises a first material
Data Source
AI summary
A device may include a first electrode, a barrier layer, and a tunneling layer having a first dielectric constant. The barrier layer may be between the first electrode and the tunneling layer. The device may also include an active layer having a second dielectric constant. The tunneling layer may be between the first electrode and the active layer. The device may further include a second electrode. The active layer may be between the tunneling layer and the second electrode.