Combo CIB Architecture for PLD Memory Logic Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable logic devices (PLDs) face inefficiencies due to the need for a common interface block (CIB) that must interface with logic, memory, and I/O blocks, leading to silicon and resource wastage, and restrict the mixing and placement of memory and logic blocks, causing routing congestion.
Innovation Solution
A programmable logic device architecture that incorporates a combo CIB, which optimally interfaces both I/O and memory blocks, reducing the number of CIBs and allowing flexible placement and mixing of memory and logic blocks, thereby optimizing connectivity and reducing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a common interface block (CIB) is designed to interface with logic blocks, memory blocks, and I/O blocks, then symmetry and ease of use are improved, but silicon area and resource efficiency deteriorate
Solution Approach 1:
The patent divides the interface functionality into separate specialized interface blocks: logic block interfaces for logic blocks, memory block interfaces for memory blocks, and I/O block interfaces for I/O blocks. Each interface block is optimized for its specific block type, eliminating the need for a generic CIB that must accommodate all block types. This segmentation reduces the silicon area required for interface blocks while maintaining ease of use through dedicated optimization for each block type.
2Ease of manufacture
If memory blocks are arranged in dedicated rows, then memory block placement is simplified, but flexibility in mixing and matching memory blocks with logic blocks deteriorates
Solution Approach 1:
The patent creates a universal interface block design that can serve multiple block types through configuration. The interface blocks are designed with programmable routing and configurable logic that can be adapted to work with logic blocks, memory blocks, or I/O blocks depending on the application requirements. This universality allows memory blocks to be placed flexibly throughout the device without being restricted to dedicated rows, while maintaining ease of manufacturing through standardized interface block designs.
3Adaptability or versatility
If separate generic CIBs are provided for memory blocks, I/O blocks, and logic blocks, then interface functionality is improved, but device complexity and routing congestion increase
Solution Approach 1:
The patent merges the functionality of separate generic CIBs into integrated interface block designs that combine the routing and interface capabilities needed for logic blocks, memory blocks, and I/O blocks into unified structures. These combined interface blocks reduce the total number of separate CIBs required in the device, thereby reducing overall device complexity and minimizing routing congestion while maintaining comprehensive interface functionality for all block types.
Data Source
AI summary
In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.