Combo Memory Cell Merging SRAM and Mask-ROM
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Solution Overview
Problem
Conventional combo memory cells require an extra transistor, increasing complexity and power consumption, and struggle to efficiently switch between random access and read-only modes.
Innovation Solution
A combo memory cell design incorporating a static random access memory (SRAM) cell and a mask read-only memory (mask-ROM) code programmer, utilizing PMOS and NMOS transistors with programmable interconnections to control voltage levels and switch between modes, reducing the need for additional transistors and optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an extra transistor is added to program the input/output nodes directly, then the ROM code can be programmed, but the device complexity increases
Solution Approach 1:
The patent merges the SRAM cell and ROM cell into a single combo memory cell structure. The mask-ROM code programmer is integrated with the SRAM cell, sharing common transistors and circuit elements. This consolidation allows both RAM and ROM functionality to coexist in one cell without requiring separate transistor sets, thereby reducing overall device complexity while maintaining programming capability.
Solution Approach 2:
The combo memory cell is designed to perform multiple functions: it can operate as a SRAM cell for random access, as a ROM cell for read-only operations, or as a fuse cell for one-time programming. The same physical structure and transistors serve multiple purposes depending on the programming state and mode selection, eliminating the need for dedicated separate structures for each function.
2Adaptability or versatility
If an extra transistor is added to control the pass transistor gate, then the mode switching between RAM and ROM is enabled, but the power consumption increases
Solution Approach 1:
The mode control functionality is merged into the existing SRAM cell structure. The mask-ROM code programmer utilizes the same transistors and circuit paths as the SRAM cell, rather than adding separate control circuits. This integration eliminates redundant power-consuming elements while maintaining the ability to switch between operational modes through selective programming of the shared structure.
3Adaptability or versatility
If separate blocks are used for RAM and ROM, then the functionality is maintained, but the chip design becomes more complex
Solution Approach 1:
The patent implements a merged SRAM-ROM cell structure where both memory types share common physical elements including transistors, interconnections, and programming circuits. The mask-ROM code programmer is integrated within the SRAM cell boundaries, allowing both RAM and ROM functionalities to coexist in a single unified cell rather than requiring separate physical blocks on the chip.
Solution Approach 2:
The combo memory cell is designed as a universal structure that can operate in multiple modes: as a standard SRAM cell for random access, as a ROM cell for read-only operations, or as a fuse cell for one-time programming. This multi-functional design eliminates the need for separate dedicated blocks for each memory type, simplifying chip architecture while maintaining full functionality of both RAM and ROM.
Data Source
AI summary
A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.