Command-Address Input Buffer Gating for Lower Memory Power Draw
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Solution Overview
Problem
Memory devices experience unnecessary power consumption due to enabled command-address input buffers when these signals are not being used, particularly during high-frequency operations.
Innovation Solution
Implementing input buffer control circuitry to selectively disable command-address input buffers based on operating mode, memory density, and connectivity/test modes, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If command-address input buffers are kept enabled to ensure signal reception capability, then reliability of signal reception is improved, but power consumption increases unnecessarily when signals are not being used
Solution Approach 1:
The patent implements dynamic control of input buffer enablement based on the memory device's operational state. The buffer control circuit selectively enables or disables command-address input buffers according to whether the device is in idle mode, active mode, self-refresh mode, or power-down mode, allowing the system to adapt its power consumption to actual operational needs while maintaining signal reception capability when required
2Loss of energy
If input buffers are disabled to reduce power consumption during idle periods, then energy efficiency is improved, but signal reception capability may be compromised if not properly managed
Solution Approach 1:
The patent employs feedback mechanisms where the buffer control circuit continuously monitors the operational mode of the memory device and adjusts input buffer enablement accordingly. This feedback loop ensures that buffers are disabled only when the device is in states where signal reception is not needed (idle, self-refresh, power-down modes), while automatically re-enabling them when active mode is detected, thus maintaining reliability while reducing energy loss
3Adaptability or versatility
If all input buffers are continuously enabled to handle any potential command signals, then adaptability to different operating modes is improved, but power consumption increases across all operations
Solution Approach 1:
The patent segments the control of different input buffers independently based on specific operational conditions. Rather than enabling all buffers uniformly, the buffer control circuit selectively enables only those buffers necessary for the current operating mode, dividing the buffer control into mode-specific subsets that are activated only when needed, thereby maintaining adaptability while reducing overall power consumption
Data Source
AI summary
Memory with command-address input buffer control is disclosed herein. In one embodiment, a memory device includes a plurality of command-address input buffers configured to receive a corresponding plurality of command-address signals of a command signal. The command signal can be received at one or more external terminals of the memory device. The memory device can further include input buffer control circuitry configured to disable one or more command-address input buffers of the plurality of command-address input buffers at times when one or more command-address signals of the plurality of command-address signals that correspond to the one or more command-address input buffers are not used. For example, the input buffer control circuitry can disable the one or more command-address input buffers based at least in part on the memory device being outside an idle mode of operation or a connectivity test being disabled while a mirror function is enabled or disabled.