Command Address Bus Timing Margin Training for Memory Modules
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Solution Overview
Problem
Conventional techniques for training command/address (C/A) buses in memory architectures are insufficient, particularly failing to effectively train the backside C/A bus, which can lead to silent data corruption due to inadequate measurement and optimization of timing margins at higher frequencies.
Innovation Solution
A method is introduced that trains both frontside and backside C/A buses by sending a sequence of commands with valid and invalid parity, enabling parity checking in DRAMs and the register clock driver (RCD), allowing for adjustment of timing parameters on internal C/A signal lines, CS signal lines, or clock lines to meet minimum margin guidelines, thereby ensuring reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signaling frequency is increased to improve throughput, then data exchange speed between memory devices and processor is improved, but the risk of errors increases due to difficulty of meeting minimum margin guidelines
Solution Approach 1:
The patent applies preliminary action by performing command signal timing margin measurements and optimizations during the training phase before actual high-frequency operation begins. The memory controller and memory device exchange training commands to measure setup and hold margins, then adjust timing parameters in advance to ensure reliable operation at the target signaling frequency, preventing errors before they occur during production data exchange.
2Ease of operation
If conventional training techniques are used for C/A buses, then frontside C/A bus training is achieved, but backside C/A bus training fails leading to silent data corruption
Solution Approach 1:
The patent applies segmentation by dividing the C/A bus into two distinct segments: frontside C/A bus (between memory controller and RCD) and backside C/A bus (between RCD and DRAMs). The training process is then separately applied to each segment using specific command sequences. Training commands are sent through the RCD to measure margins on the backside bus independently, ensuring both segments are properly trained and preventing silent data corruption that would occur if only the frontside bus were trained.
Data Source
AI summary
Techniques for training a command/address (C/A) bus, including training internal command/address (C/A) signal lines of a memory module are described. In one example, a method of training a C/A bus involves a memory controller transmitting a first command to a DRAM with parity checking enabled, the first command to include valid parity and chip select asserted. The memory controller transmits commands in cycles before and after the first command to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted. In response to detecting a parity error, the memory controller modifies a timing parameter to adjust timing for the internal C/A signal lines of the memory module.