Command Address Channel Error Detection Circuit
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Solution Overview
Problem
Current memory systems face challenges in accurately detecting errors during command and data transmission between controllers and memory components, leading to potential data corruption and incorrect operations.
Innovation Solution
The implementation of error-detection code (EDC) calculation and comparison circuits in both controllers and memory components, using cyclic redundancy check (CRC) values and exclusive-OR operations to ensure data integrity by comparing calculated EDC values across both systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-detection code calculation and comparison circuits are implemented in both controllers and memory components, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by calculating error-detection codes (EDC) in advance for command information before transmission. The controller calculates an EDC value for the command information and transmits it along with the command to the memory component, which then compares this pre-calculated EDC with its own calculation to detect errors.
Solution Approach 2:
The patent uses an intermediary approach by introducing EDC values as mediators between the controller and memory component. The EDC values are calculated by both parties independently and then compared to verify data integrity, serving as an intermediate verification mechanism without requiring complex direct verification circuits.
2Measurement precision
If EDC values are transmitted between controller and memory component, then error detection accuracy is improved, but loss of time increases
Solution Approach 1:
The patent merges the EDC value transmission with the existing command information transmission protocol. The EDC values are transmitted along with the command information using the same communication interface and protocol, consolidating multiple data streams into a single transmission process to minimize additional time overhead.
Solution Approach 2:
The patent implements partial action by transmitting EDC values selectively for error detection rather than retransmitting all command information. Only the critical EDC values are transmitted and compared, performing just enough verification to detect errors without redundant transmissions.
Data Source
AI summary
A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.