Command Address Fault Detection in Memory Devices
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Solution Overview
Problem
Current memory devices face challenges in detecting and correcting command and address-related faults on the command/address (CA) bus, leading to undetected failures that exceed safety thresholds in critical applications like autonomous vehicles, where errors can compromise safety.
Innovation Solution
A system where a host device generates and transmits a CA word and parity bits to a memory device, which compares these with locally generated parity bits to detect errors, activating an alert signal for corrective actions, thereby improving fault detection and reducing FIT rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory devices operate without command address fault detection, then device complexity is reduced, but reliability deteriorates due to undetected failures exceeding safety thresholds
Solution Approach 1:
The host device generates parity bits for the CA word in advance before transmission to the memory device. This preliminary action allows the memory device to perform fault detection by comparing received parity bits with locally generated ones, thereby improving reliability without requiring complex detection circuitry within the memory device itself.
Solution Approach 2:
Parity bits serve as an intermediary mechanism for fault detection. The host device generates these parity bits based on the CA word and transmits them to the memory device, which then uses them to detect command address faults. This intermediary approach enables reliable fault detection while maintaining relatively simple device architecture.
2Reliability
If parity bits are transmitted over the CA bus, then fault detection capability is improved, but loss of information increases due to potential corruption of transmitted data
Solution Approach 1:
The memory device performs feedback by comparing the received parity bits with locally generated parity bits based on the received CA word. This feedback mechanism enables the memory device to detect whether the CA word or parity bits were corrupted during transmission, thereby identifying information loss and preventing undetected failures.
Solution Approach 2:
By transmitting parity bits along with the CA word and performing immediate comparison, the system applies preliminary anti-action to prevent corrupted data from being processed. When a mismatch is detected, the system can identify the corruption before it causes incorrect memory operations, thereby counteracting the potential harm of information loss.
3Ease of operation
If command address faults are not detected, then ease of operation is maintained, but harmful factors increase due to undetected errors compromising safety in critical applications
Solution Approach 1:
The memory device performs self-service by autonomously generating local parity bits and comparing them with received parity bits to detect command address faults. This self-service approach enables the memory device to independently identify errors without requiring complex external detection systems, maintaining ease of operation while eliminating safety risks from undetected faults.
Data Source
AI summary
Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.