Command Address Latching for Semiconductor Setup Hold Time Control

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Solution Overview

Problem

In semiconductor devices, when the number of command/address signals exceeds the number of data pads, it becomes impossible to output these signals, thereby preventing the controller from controlling the setup/hold times, which are crucial for operational efficiency.

Innovation Solution

A semiconductor system that divisionally latches command/address signals, utilizing a controller and semiconductor device configuration including a signal generation block, latch block, selective latch block, read path circuit, and multiplexer to generate and control latched command addresses, even when the number of command addresses exceeds the number of data pads, allowing for the transmission and control of setup/hold times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the number of command/address signals is increased to meet higher operating speeds, then the operating speed is improved, but the setup/hold time control capability deteriorates when the number of signals exceeds the number of data pads

Engineering Contradiction:
Improveoperating speedVSAvoidsetup/hold time control capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent divides the command/address signals into multiple groups, with each group assigned to a different data pad for output. This segmentation allows the system to handle more command/address signals than there are data pads, while maintaining the ability to measure delay amounts and control setup/hold times for each group independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism where the semiconductor device outputs latched command/address signals through data pads, and the controller uses these outputs to calculate delay amounts. This intermediary approach enables indirect measurement and control of setup/hold times even when direct output of all command/address signals is not possible.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the number of command/address signals exceeds the number of data pads, then signal coverage is improved, but the feedback capability for setup/hold time control is lost

Engineering Contradiction:
Improvesignal coverageVSAvoidfeedback capability
Core Design Contradiction:
Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent uses a copying approach where the semiconductor device latches command/address signals and outputs them through data pads. The controller receives these copied signals and uses them to calculate delay amounts and control setup/hold times, maintaining feedback capability even when the number of command/address signals exceeds the number of data pads.

Inventive Principle:
Principle #26Copying

3Ease of operation

If all command/address signals are latched simultaneously, then the latching operation is simplified, but the setup/hold time control precision deteriorates

Engineering Contradiction:
Improvelatching operation simplicityVSAvoidsetup/hold time control precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent segments command/address signals into multiple groups that are latched at different times through different data pads. This segmentation allows for precise measurement of delay amounts for each group, improving setup/hold time control precision while maintaining reasonable operational simplicity through systematic grouping.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8675426B2Semiconductor device, semiconductor system having the same, and command address setup/hold time control method therefor
Publication Date: 2014.03.18 SK HYNIX INC
  • US8675426B2 patent drawing
  • US8675426B2 patent drawing
  • US8675426B2 patent drawing

AI summary

A semiconductor system includes a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal.