Command-Aware Hardware Routing Mesh for FPGA and ASIC Integration
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Solution Overview
Problem
Current computer architectures lack a common design system for FPGA and ASIC-based platforms, making it difficult to combine compute modules developed by different developers and leading to variability in performance and stability due to the need for expensive and complex changes to accommodate modified or added compute functions.
Innovation Solution
A hardware routing mesh with routing nodes and associated hardware modules that dynamically process command bundles, allowing for the modification and optimization of compute functions by rearranging routing nodes and executing commands in parallel across multiple hardware modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compute functions are offloaded to FPGA/ASIC platforms, then processing power and performance are improved, but device complexity and difficulty of modification increase
Solution Approach 1:
The system segments compute functions into discrete command bundles that can be independently processed by different hardware modules. Each command bundle represents a modular unit of computation that can be routed to appropriate FPGA/ASIC hardware modules, allowing the system to achieve high processing power through parallel execution while maintaining manageability through functional segmentation.
Solution Approach 2:
The patent creates a universal command bundle interface that can be executed across multiple types of hardware modules (CPU, GPU, FPGA, ASIC). This universal interface layer allows the system to leverage diverse hardware platforms for accelerated processing while presenting a consistent programming model to developers, thereby improving productivity without proportionally increasing device complexity.
2Adaptability or versatility
If compute modules are modified or added to FPGA/ASIC platforms, then functionality is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The system employs dynamic routing nodes that can be reconfigured at runtime to route command bundles to different hardware modules based on current computational needs. This dynamic adaptability allows the FPGA/ASIC platform to change its functional configuration without physical remanufacturing, enabling functionality modifications through software-controlled routing rather than hardware redesign, thereby maintaining ease of manufacture.
Solution Approach 2:
The patent pre-compiles compute functions into standardized command bundles that encode operational parameters and routing information. This preliminary preparation of commands allows the hardware platform to execute new functions simply by loading pre-compiled command bundles and reconfiguring routing nodes, rather than requiring expensive remanufacturing processes, thus achieving adaptability while preserving manufacturing economy.
3Productivity
If compute functions are distributed across multiple hardware modules, then processing efficiency is improved, but system complexity increases
Solution Approach 1:
The patent introduces routing nodes as intermediary components that manage communication and data flow between multiple hardware modules. These routing nodes receive command bundles, determine appropriate destination modules based on command type and hardware availability, and coordinate data transfer. This intermediary layer enables efficient parallel processing across multiple hardware modules while abstracting the complexity of inter-module coordination from the overall system.
4Productivity
If routing nodes are rearranged to optimize command processing, then performance is improved, but control complexity increases
Solution Approach 1:
The routing nodes are designed with self-service capabilities, automatically analyzing incoming command bundles and autonomously determining optimal routing paths based on command characteristics and current hardware module availability. The routing nodes perform self-configuration and adaptive rearrangement without requiring external control intervention, thereby achieving performance optimization through dynamic routing while keeping control complexity minimal.
Data Source
AI summary
In an embodiment, responsive to determining: (a) a first command is not of a particular command type associated with one or more hardware modules associated with a particular routing node, or (b) at least one argument used for executing the first command is not available: transmitting the first command to another routing node in the hardware routing mesh. Upon receiving a second command of the command bundle and determining: (a) the second command is of the particular command type associated with the hardware module(s), and (b) arguments used by the second command are available: transmitting the second command to the hardware module(s) associated with the particular routing node for execution by the hardware module(s). Thereafter, the command bundle is modified based on execution of the second command by at least refraining from transmitting the second command of the command bundle to any other routing nodes in the hardware routing mesh.