Command Bus Training Using Parity Feedback for DDR Memory
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Solution Overview
Problem
Existing command bus training methods for LPDDR4 and LPDDR5 memory devices are slow and require significant firmware coordination, limiting the number of samples that can be tested and impacting training quality due to the need for iterative software-based processes.
Innovation Solution
Implementing command address training mode (CATM) for DDR5 memory devices, which uses internal circuitry to return parity values for error checking, and utilizing error detection circuitry in the memory controller to simplify command bus training by reducing the need for firmware coordination and increasing the speed and quality of training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If firmware coordination is used for command bus training in LPDDR4 and LPDDR5 devices, then training can be performed with iterative testing of I/O parameters, but the training process becomes slow and requires significant firmware involvement
Solution Approach 1:
The memory device performs self-diagnosis by using its internal circuitry to detect errors in received command/address patterns and autonomously generates parity values to communicate error status back to the memory controller, eliminating the need for firmware-based iterative testing
Solution Approach 2:
The patent replaces the firmware-based software control mechanism with hardware-based error detection circuitry that continuously monitors and detects signaling errors on the command bus, enabling faster and more efficient training
2Measurement precision
If firmware coordination is used for command bus training, then iterative testing of different I/O interface parameters can be performed, but the number of samples that can be tested is limited
Solution Approach 1:
The memory device autonomously performs error detection and generates parity values for multiple command patterns simultaneously without requiring firmware intervention for each test, dramatically increasing the number of samples that can be evaluated
Solution Approach 2:
The error detection circuitry operates continuously during command bus training, allowing uninterrupted testing of multiple I/O parameters and patterns without the stop-start nature of firmware-based iterative testing
Data Source
AI summary
Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.