Command Control Circuit With Error-Gated Internal Command Blocking

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Solution Overview

Problem

Conventional integrated circuits face increased circuit area and power consumption due to the need for multiple flip-flops to synchronize commands and addresses during error checking, which becomes cumbersome as the number of commands and addresses increases.

Innovation Solution

A command control circuit with a blocking unit that blocks or passes internal commands based on error check signals, reducing the need for synchronous delay circuits and using an asynchronous delay circuit to minimize circuit area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple flip-flops are used to synchronize commands and addresses during error checking, then the error check reliability is improved, but the circuit area and power consumption increase

Engineering Contradiction:
Improveerror check reliabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the synchronization function from the error checking path by using a separate synchronization delay unit that operates independently. This allows the error check unit to generate error check signals without requiring multiple flip-flops for synchronization, thereby reducing circuit area while maintaining error checking reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The synchronization delay unit performs preliminary delay of commands and addresses before they reach the error check unit. This preliminary action ensures that error check signals are generated at the correct timing without requiring complex synchronization mechanisms during the error checking process itself.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple flip-flops are used to synchronize commands and addresses during error checking, then the error check reliability is improved, but the power consumption increases

Engineering Contradiction:
Improveerror check reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the synchronization function from the error checking path by using a separate synchronization delay unit that operates independently. This allows the error check unit to generate error check signals without requiring multiple flip-flops for synchronization, thereby reducing power consumption while maintaining error checking reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If the number of commands and addresses increases, then the functionality is improved, but the circuit area increases due to more flip-flops

Engineering Contradiction:
ImprovefunctionalityVSAvoidcircuit area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The synchronization delay unit serves multiple functions: it delays commands, delays addresses, and provides synchronization for the error checking mechanism. This multi-functionality allows the system to handle increased numbers of commands and addresses without proportionally increasing circuit area, as the same delay mechanism serves multiple purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8566685B2Command control circuit, integrated circuit having the same, and command control method
Publication Date: 2013.10.22 SK HYNIX INC
  • US8566685B2 patent drawing
  • US8566685B2 patent drawing
  • US8566685B2 patent drawing

AI summary

A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.