Command Clock Gating with Chip Select Signal Training
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Solution Overview
Problem
In memory devices, the synchronization between the internal clock signal and the chip select clock signal is unknown due to the device topology, leading to unpredictable timing specifications, which prevents effective command clock gating and training of the chip select and command address signals.
Innovation Solution
A register is used to indicate the training state of the chip select clock and/or command address buffer, allowing synchronization with the internal clock signal, and a clock gating circuitry is employed to gate the internal clock based on this training indication, ensuring proper capture of valid commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If command clock gating is implemented using chip select signal, then power consumption is reduced, but the internal clock signal cannot be properly gated due to unknown timing relationship with chip select signal
Solution Approach 1:
The patent performs training operations before normal operation to establish the timing relationship between internal clock signal and chip select signal. The training sequence determines optimal delay values that are stored and used during subsequent normal operation, enabling reliable clock gating without sacrificing command capture reliability
Solution Approach 2:
The patent dynamically adjusts delay parameters in the clock gating circuitry based on training results. By changing the delay value parameter to match the actual timing relationship between internal clock and chip select signal, the system achieves both power savings from clock gating and reliable command capture
2Reliability
If training sequence is implemented to establish timing relationship, then clock gating reliability is improved, but additional training time and complexity are required
Solution Approach 1:
The training sequence is executed during initialization or setup phase before the memory device begins normal operation. By completing the time-consuming training process beforehand, the optimal timing parameters are established once and then reused during normal operation without recurring training overhead
Solution Approach 2:
The training process is integrated into the device's self-initialization routine, allowing the device to automatically determine its own timing parameters without requiring external intervention or additional system resources. The device self-configures the delay values based on its internal timing characteristics
3Adaptability or versatility
If chip select signal timing is unknown due to device topology, then device flexibility is maintained, but effective command clock gating cannot be achieved
Solution Approach 1:
The patent transforms the fixed, unknown timing relationship into a variable, measurable parameter through training. By determining the actual delay value and configuring the clock gating circuitry accordingly, the system adapts to the specific device topology while enabling power-saving clock gating functionality
Solution Approach 2:
The training process provides feedback about the actual timing relationship between internal clock and chip select signal. This feedback information is used to configure the clock gating circuitry with the correct delay value, creating a closed-loop system that adapts to device-specific timing characteristics
Data Source
AI summary
Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.