Command Converter Buffering for Memory Access Granularity Mismatch

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Solution Overview

Problem

Existing memory designs face challenges such as granularity incompatibility, low bandwidth utilization, long latency, high power consumption, and inefficient data buffering, particularly in wide-IO interfaces for 3D integrated circuits and solid-state drives.

Innovation Solution

A command converter system comprising a first buffer, an address list, and a logic circuit that converts access requests from a first granularity to a second, larger granularity, optimizing data transfers and reducing write amplification and read disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If NAND devices are used to accommodate wide-IO interface, then storage capacity is improved, but granularity incompatibility occurs

Engineering Contradiction:
Improvestorage capacityVSAvoidgranularity compatibility
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent introduces a command converter as an intermediary device between the host processor and NAND flash memory. This converter includes a buffer that stores data and an address list that tracks storage locations. The command converter translates wide-IO interface requests into NAND-compatible commands, matching data to appropriate storage locations and combining multiple small writes into larger programmed writes. This intermediary resolves the granularity incompatibility between the wide-IO interface and NAND devices while preserving high storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If direct access to NAND devices is implemented, then device complexity is reduced, but bandwidth utilization decreases

Engineering Contradiction:
Improveinterface complexityVSAvoidbandwidth utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The command converter performs preliminary actions by pre-processing write requests before they reach the NAND devices. The buffer accumulates incoming data and the address list pre-organizes storage locations. Multiple small write requests are combined into larger programmed writes in advance, maximizing NAND device utilization. This preliminary processing maintains simple direct access while achieving high bandwidth utilization through intelligent data aggregation.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If frequent page open and close operations are performed, then access flexibility is improved, but power consumption increases

Engineering Contradiction:
Improveaccess flexibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The command converter merges multiple small write requests into larger programmed writes. The buffer accumulates data and the address list tracks which pages need writing. Instead of immediately opening and closing pages for each small write, the converter combines requests and performs bulk programmed writes, reducing the frequency of page open/close operations. This merging strategy maintains access flexibility while significantly reducing power consumption associated with page management operations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4687019A1Command converter for granularity incompatibility in memory accesses
Publication Date: 2026.02.04 SAMSUNG ELECTRONICS CO LTD
  • EP4687019A1 patent drawingFigure 1
  • EP4687019A1 patent drawingFigure 2
  • EP4687019A1 patent drawingFigure 3

AI summary

A command converter for interfacing to a wide-IO solid-state storage is disclosed. A first buffer (436) is configured to store first data of a first access type from an access request device (282) having a first granularity. An address list (432) is configured to store at least one address of the first data and to have at least a first status and a second status associated with the at least one address. An access matcher (428) is configured to generate an access result based on a comparison of a request address and the at least one address in the address list (432). A logic circuit (426) is configured to perform an action based on at least one of the access result, the first status, or the second status. The action includes combining the first data into a second data of a second access type having a second granularity larger than the first granularity.