Command Decoder Error Detection via Delayed Control Word Comparison
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Solution Overview
Problem
Instruction decoders face reliability issues due to volatile bit errors during the reading of control signal words from memory, leading to potential incorrect execution of instructions, especially when dealing with status signals and parameters that affect the sequences of control words.
Innovation Solution
An error detection device and method that compares sequences of control signal words read at different times or generates and compares signatures to detect errors, ensuring correct execution by repeating instructions if errors are found, and optionally using dual ALUs or sign extension units for enhanced protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control signal words are read from memory without verification, then the instruction execution speed is maintained, but bit errors occur leading to wrong sequences and incorrect instruction execution
Solution Approach 1:
The patent applies preliminary action by generating a signature of the control signal sequence immediately after reading from memory, before execution. This allows error detection to occur proactively rather than reactively, enabling the system to identify corrupted sequences and request re-reading without interrupting the overall execution flow significantly.
Solution Approach 2:
The patent implements feedback through the signature verification mechanism. The generated signature is compared against expected values, and when errors are detected, the system provides feedback by triggering a re-read of the control signal sequence. This closed-loop feedback ensures reliability while maintaining throughput through parallel error handling.
2Reliability
If control signal sequences are verified by reading and comparing, then errors are detected, but the verification process takes additional time
Solution Approach 1:
The patent replaces the mechanical approach of reading and comparing entire control signal sequences with a signature-based verification system. Instead of comparing multiple sequences, the system generates a compact signature (hash or checksum) of the control signal sequence and compares this condensed representation, dramatically reducing verification time while maintaining error detection capability.
Solution Approach 2:
The patent changes the parameter representation from full control signal sequences to condensed signatures. This parameter transformation allows verification to operate on much smaller data structures, reducing the time complexity from O(n) to O(1) for the comparison operation while preserving the ability to detect errors through the mathematical properties of signature generation functions.
3Adaptability or versatility
If multiple sequences of control signal words are associated with an instruction based on status signals, then the decoder can handle complex instructions, but the complexity of determining the correct sequence increases
Solution Approach 1:
The patent applies copying by generating multiple candidate control signal sequences corresponding to different status signal conditions, then using signature verification to identify the correct one. Instead of implementing complex logic to determine which sequence to execute, the system generates copies of possible sequences, verifies them through signature comparison, and executes the validated sequence.
Solution Approach 2:
The patent implements universality through a single signature verification mechanism that works across all instruction types and status signal combinations. The same signature generation and comparison logic handles simple and complex instructions uniformly, eliminating the need for separate verification paths and reducing overall decoder complexity despite supporting multiple sequences.
Data Source
AI summary
An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein the sequence of control signal words has at least one control signal word, having: a controller designed to provide the input word at a first time and the input word at a second time for reading out the command memory, wherein the second time is delayed with respect to the first time, to effect a readout of the sequence of control signal words at a first time and a readout of the sequence of control signal words at a second time; and a comparator designed to receive and compare the associated sequences of control signal words read out at the first and second times, and to output a signal indicating an error if the associated sequences of control signal words read out at the first and second times are different.