Command Decoding Circuit with Pre-Trigger Signal Generation
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Solution Overview
Problem
Conventional command decoders in memory devices experience inefficiencies due to time delays in generating the starting signal for operations, which limits the frequency of the external clock signal and overall device efficiency.
Innovation Solution
A decoding circuit and method that includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit to generate a starting signal earlier by comparing former and latter encoded data of the received command with predetermined data, allowing for earlier initiation of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional command decoder is used with sequential decoding process, then decoding accuracy is maintained, but starting signal generation is delayed by sum of time delays t1, t2, and t3
Solution Approach 1:
The patent applies preliminary action by generating a pre-trigger signal in advance based on the first four bits of command data before the complete eight bits are received. This pre-trigger signal is generated at time T1 when only partial data is available, rather than waiting for complete decoding. The pre-trigger signal initiates preliminary operations while the remaining command bits are being decoded, thereby reducing the overall delay without sacrificing final decoding accuracy through the subsequent match signal validation.
2Productivity
If clock signal frequency is increased to improve efficiency, then device throughput increases, but time period for operation execution becomes insufficient
Solution Approach 1:
The patent resolves this contradiction by performing preliminary actions earlier in the clock cycle. The pre-trigger signal is generated based on the first four bits of command data at time T1, which is earlier than the conventional approach that waits for all eight bits. This advanced timing creates a longer effective time period P for operation execution, allowing the system to use higher clock frequencies while maintaining sufficient operation duration.
3Productivity
If external clock signal frequency is increased, then memory device efficiency improves, but setup time and hold time requirements cannot be met
Solution Approach 1:
The patent applies preliminary action by using the first four bits of command data to generate a pre-trigger signal before the complete command is received. This early generation of the pre-trigger signal advances the timing of operation initiation, creating additional time buffer that allows setup time and hold time requirements to be satisfied even at higher clock frequencies. The system performs useful work in advance rather than waiting for complete data arrival.
Data Source
AI summary
A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.