Command-Prefetching Asynchronous Bridge for Cross-Clock Processing

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Solution Overview

Problem

Existing asynchronous bridges struggle to optimize performance when handling communication between devices operating at different clocks, such as a digital signal processor (DSP) and a central processing unit (CPU), due to inefficiencies in command processing.

Innovation Solution

An asynchronous bridge equipped with a command receiver and a command prefetcher that prefetched commands before execution completion, utilizing a prefetch buffer and command processor to manage and prioritize requests, ensuring devices operate efficiently despite different clock frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If commands are processed sequentially after execution completion, then device operation simplicity is maintained, but system performance and latency are degraded

Engineering Contradiction:
Improvesystem performanceVSAvoidcommand processing latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The command prefetcher proactively captures and buffers commands from the first-clock computing device before they are formally issued to the second-clock computing device. By performing preliminary command capture and buffering, the system eliminates waiting time during clock domain transitions, thereby improving system performance without complicating the core device operation.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If command prefetching is implemented, then command processing latency is reduced, but device complexity increases

Engineering Contradiction:
Improvecommand processing latencyVSAvoidasynchronous bridge structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces a command prefetcher and prefetch buffer as intermediary components between the first-clock and second-clock computing devices. These intermediaries handle the complex task of command capture, buffering, and timing synchronization, allowing the core computing devices to remain simple while benefiting from reduced latency through the intermediary's preprocessing capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data is transferred synchronously between clock domains, then timing synchronization is simplified, but processing efficiency is reduced

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidclock domain synchronization
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The command prefetcher performs preliminary command capture and the prefetch buffer stores commands before they need to be executed in the second clock domain. This preliminary action allows data transfer to begin before the receiving device is ready, eliminating idle waiting time and improving transfer efficiency without requiring complex real-time synchronization mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12405913B2Asynchronous bridge, and asynchronous processing method
Publication Date: 2025.09.02 NUVOTON
  • US12405913B2 patent drawing
  • US12405913B2 patent drawing
  • US12405913B2 patent drawing

AI summary

An asynchronous bridge with command prefetching, including a command prefetcher as well as a command receiver. The command receiver receives a first command from a first-clock computing device. The first command is issued to operate a second-clock computing device. The command prefetcher prefetches a second command from the first-clock computing device before the first-clock computing device receives notice of execution completion of the first command. In this manner, when the command receiver receives the second command (that the first-clock computing device formally issues to operate the second-clock computing device), the second-clock computing device already operates in response to the prefetched second command.