Command Processing Circuit Clock Gating for Memory Power Reduction
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Solution Overview
Problem
As memory devices evolve to operate at higher speeds, processing command signals within each clock cycle becomes increasingly difficult, leading to increased power consumption due to the need for multiple processing units in a time-interleaved scheme.
Innovation Solution
A command processing circuit that includes a clock divider generating divided clock signals with lower frequency and distinct phases, a clock controller that synchronizes the command signal with the external clock, and a command decoder that decodes the signal using an operating clock signal with reduced frequency and phase alignment, allowing for efficient processing and reduced power consumption by activating only the necessary clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple command processing units are used in a time-interleaved scheme to process command signals at higher speeds, then the processing speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal is selectively enabled or disabled based on whether command signal processing is currently required. The clock control circuit monitors the operational state of the command processing unit and adjusts the clock signal accordingly, allowing the system to transition between active and low-power states dynamically. This resolves the contradiction by enabling high-speed processing when needed while minimizing power consumption during idle periods.
Solution Approach 2:
The patent employs periodic clock gating where the clock signal is interrupted in a periodic manner based on the processing requirements. Instead of providing continuous clock signals to all processing units, the system activates clock signals only during specific time periods when command processing is required, creating a periodic pattern of high-performance operation followed by low-power states. This approach maintains processing speed capability while reducing average power consumption.
2Loss of time
If command signals are processed within each clock cycle to meet timing requirements, then the processing timing is improved, but the power consumption increases due to continuous operation
Solution Approach 1:
The patent implements preliminary clock gating control where the clock signal is enabled in advance before command signal processing is required and disabled after processing completes. The clock control circuit anticipates processing needs and prepares the clock signal accordingly, ensuring that when processing begins, the clock is already active and ready to drive the processing unit at full speed. This eliminates startup delays while avoiding unnecessary continuous operation that would increase power consumption.
3Speed
If multiple divided clock signals with different phases are generated to handle high-speed operations, then the processing capability is improved, but the device complexity increases
Solution Approach 1:
The patent extracts and isolates the clock control functionality into a dedicated clock control circuit that separately manages the clock gating logic. By removing the complex phase management and clock distribution logic from the main command processing path and placing it in a dedicated control unit, the system achieves high-speed operation with multiple phased clock signals while reducing the complexity burden on the core processing architecture. The clock control circuit handles the complexity of managing multiple divided clock signals independently.
Data Source
AI summary
A command processing circuit of a memory device includes a clock divider, a clock controller and a command decoder. The clock divider generates a plurality of divided clock signals based on an external clock signal having a first frequency. The divided clock signals have a second frequency lower than the first frequency. Each of the divided clock signals has a phase that is different from phases of the other divided clock signals. The clock controller generates an operating clock signal based on a command signal and the divided clock signals, where the command signal is transferred in synchronization with the external clock signal. The operating clock signal has the second frequency and a phase corresponding to reception timing of the command signal. The command decoder decodes the command signal in synchronization with the operating clock signal.