Command Processor Deferred Execution for Latency Reduction
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Solution Overview
Problem
Command execution latency in computing devices is increased due to time delays caused by stopping and resuming command processing when fetching commands from secondary buffers, leading to cumulative delays in the command execution flow.
Innovation Solution
The command processor defers the execution of commands between first and second links in the main buffer, allowing for simultaneous fetching of commands associated with both links, thereby overlapping fetching procedures to reduce execution latency and maintain correct flow order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If commands are fetched sequentially from main memory to on-chip memory, then command execution order is maintained, but cumulative time delay increases due to repeated stopping and resuming of command execution
Solution Approach 1:
The command processor identifies links to secondary buffers in advance during command fetching and initiates fetching of those secondary buffers before the main buffer commands are fully executed. This preliminary action allows overlapping of fetch operations, reducing the cumulative time delay caused by sequential fetching while maintaining correct execution order through deferred execution of intermediate commands.
2Reliability
If command execution is stopped to fetch secondary buffer commands, then correct flow order is maintained, but execution latency increases due to repeated stopping and resuming
Solution Approach 1:
The command buffer is segmented into main buffer and multiple secondary buffers, each with distinct command sets. The command processor executes commands from the main buffer and, upon identifying links to secondary buffers, fetches those secondary buffer commands in advance. This segmentation allows parallel fetching operations while maintaining execution order through a deferred execution mechanism that tracks which commands have been fetched and when they should be executed.
3Ease of manufacture
If multiple secondary buffers are fetched sequentially, then memory bandwidth is managed, but fetching time increases reducing overall processing efficiency
Solution Approach 1:
The command processor maintains continuous useful action by overlapping fetch operations. While commands from the main buffer are being executed, the processor simultaneously initiates fetching of multiple secondary buffers in parallel where possible, rather than completing one fetch entirely before starting the next. This continuous overlapping of fetch and execute operations maximizes memory bandwidth utilization and reduces total fetching time.
Data Source
AI summary
Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.