Command Processor Packet Attribute Validation for Parallel Processing Security

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Solution Overview

Problem

Existing computing systems face difficulties in distinguishing between malicious and legitimate communications, leading to potential execution of malformed data packets that can cause unsynchronized operations in parallel processing units, resulting in system malfunctions or data corruption.

Innovation Solution

A method and system for packet attribute confirmation, where a command processor in a parallel processor receives a command packet, compares its size with an expected size, and passes matching commands to a prefetch parser or no-operation instructions to prevent execution of mismatched packets, ensuring only well-formed packets are executed, thereby preventing malicious or malformed data from causing system unsynchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If packet size validation is implemented to prevent malicious data execution, then system reliability is improved, but processing speed deteriorates due to additional comparison operations

Engineering Contradiction:
Improvesystem reliabilityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs packet size validation in advance before executing the packet contents. The command processor compares the received packet size against the expected packet size defined in the jump table before routing the packet to execution units. This preliminary validation prevents malicious or malformed packets from causing system malfunctions while maintaining processing efficiency by filtering invalid packets early in the pipeline.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If all received command packets are executed without validation, then processing productivity is maintained, but system security deteriorates allowing malicious programming execution

Engineering Contradiction:
Improveprocessing productivityVSAvoidmalicious programming
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary validation mechanism between packet reception and execution. The command processor acts as an intermediary that intercepts received command packets, validates their size attributes against expected values from the jump table, and only permits valid packets to proceed to execution units. This intermediary layer blocks malicious programming while allowing legitimate packets to execute, thus maintaining productivity without compromising security.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If packet size comparison and validation logic is added to the command processor, then system resilience against malicious data is improved, but device complexity increases

Engineering Contradiction:
Improvesystem resilienceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates packet size validation functionality into the existing command processor architecture, making the command processor multi-functional. The same command processor that routes and executes commands also performs size validation by comparing received packet sizes against expected values stored in the jump table. This universal approach avoids adding separate validation hardware, thereby improving resilience without significantly increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11809558B2Hardware security hardening for processor devices
Publication Date: 2023.11.07 ADVANCED MICRO DEVICES INC
  • US11809558B2 patent drawing
  • US11809558B2 patent drawing
  • US11809558B2 patent drawing

AI summary

A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.