Command Processor Replay Buffer for Co-Simulation Bottlenecks

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Solution Overview

Problem

In hardware co-simulation systems, the communication channel often becomes a bottleneck due to significant data transfer overhead, limited bandwidth, and latency, which hampers the efficiency of testing circuit designs in integrated circuit devices.

Innovation Solution

An integrated circuit with a command processor and a replay buffer that stores command templates, along with a command FIFO memory, allows for the selective provision of complementary data to form complete commands, reducing the need for repeated data transfer by preloading recurring data patterns into the replay buffer during hardware co-simulation sessions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transferred between host and PLD during hardware co-simulation, then commands and data can be exchanged for testing, but communication channel bandwidth is limited and latency increases

Engineering Contradiction:
Improvehardware co-simulation efficiencyVSAvoiddata transfer time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The replay buffer is preloaded with command templates before the hardware co-simulation session begins. During simulation, these pre-stored templates are retrieved and completed with current data from the command FIFO, eliminating the need to retransmit complete command sequences and significantly reducing data transfer time during the simulation process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Commands are segmented into two parts: command templates stored in the replay buffer and current data obtained from the command FIFO. This segmentation allows only the essential template information to be pre-loaded while current data is fetched as needed, reducing the volume of data transferred over the communication channel

Inventive Principle:
Principle #1Segmentation

2Reliability

If complete commands are transferred from host to PLD, then all necessary information is provided, but data transfer overhead increases significantly

Engineering Contradiction:
Improvecommand completenessVSAvoiddata transfer volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Each command is divided into a template portion (stored in replay buffer) and a data portion (fetched from command FIFO). The template contains the command structure and type information, while only the necessary current data is transferred from the host via the command FIFO, significantly reducing the total data volume while maintaining command completeness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Command templates are copied into the replay buffer before the simulation session. During execution, these templates are retrieved and combined with current data from the command FIFO to form complete commands, eliminating the need to retransmit the complete command structure repeatedly

Inventive Principle:
Principle #26Copying

3Ease of operation

If communication protocol overhead is used for data transfer, then proper data exchange is enabled, but additional time and data are required apart from actual test data

Engineering Contradiction:
Improvedata exchange capabilityVSAvoidprotocol setup and teardown time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The replay buffer is configured and preloaded with command templates before the hardware co-simulation session begins. During the simulation, the command processor retrieves templates from the replay buffer and combines them with current data from the command FIFO, eliminating the need for repeated protocol setup and teardown operations and reducing overall communication overhead

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7930162B1Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor
Publication Date: 2011.04.19 XILINX INC
  • US7930162B1 patent drawing
  • US7930162B1 patent drawing
  • US7930162B1 patent drawing

AI summary

An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.