Command Register Group for Calculation Processing Apparatus
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Solution Overview
Problem
The existing calculation processing apparatus outside the processor faces inefficiencies in data transfer due to processor load and interrupt notifications, leading to decreased data transfer efficiency between the processor's address space and the calculation processing apparatus's exclusive memory, particularly when handling multiple commands and operations simultaneously.
Innovation Solution
A calculation processing apparatus with a state machine that manages processing states for both data transfer and calculation units, allowing commands to be fed based on their specific states and elapsed times, utilizing a command register group and control unit to optimize command execution and reduce processor load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor directly performs control by interruption for calculation processing apparatus, then the processor can respond to calculation requests, but the processor load increases and data transfer efficiency decreases
Solution Approach 1:
A command buffer is introduced as an intermediary between the processor and the calculation processing apparatus. The command buffer stores control contents (commands) that the processor writes in advance, and feeds these commands to the calculation processing apparatus upon interrupt notification. This intermediary structure allows the processor to offload continuous control tasks, reducing processor load while maintaining efficient data transfer through automated command feeding.
Solution Approach 2:
The processor writes a plurality of control contents determined in advance into the command buffer before actual execution. This preliminary action allows the command buffer to have processing contents ready to feed immediately upon interrupt notification, eliminating waiting time and ensuring continuous operation of the calculation processing apparatus without requiring the processor to be continuously engaged.
2Productivity
If the command buffer feeds processing contents immediately upon interrupt notification, then the DMA transfer efficiency improves, but the command buffer configuration becomes complex when controlling multiple functions
Solution Approach 1:
The command buffer is segmented into multiple command columns, where each command column independently stores and manages a complete set of control contents for a specific calculation task. This segmentation allows the command buffer to handle multiple functions and tasks simultaneously through independent command columns, reducing the complexity of managing multiple functions within a single unified structure while maintaining continuous feeding capability for each task.
3Device complexity
If the command buffer controls the whole calculation processing apparatus including DMA transfer unit and calculation unit, then the processor load is reduced, but the command buffer needs to accurately interpret control contents and know calculation progress status
Solution Approach 1:
The control functionality is segmented between the command buffer and the calculation processing apparatus. The command buffer stores control contents without needing to interpret them or track calculation progress. The calculation processing apparatus independently interprets the control contents from its command column and manages its own execution progress. This segmentation reduces the command buffer's complexity to simple storage and feeding operations while maintaining comprehensive control capability.
Data Source
AI summary
A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.