Command Reorder Device with Retry Function for Memory Access
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Solution Overview
Problem
Existing memory access performance is hindered by the output order of commands in a FIFO buffer, and errors during command transmission can lead to inefficient retry mechanisms, often resulting in underutilization of retry queues.
Innovation Solution
A command reorder device with a retry function is introduced, which includes a first switch circuit, multiple command buffers, a second switch circuit, and a queue control circuit. This device reorders commands based on a reorder policy and integrates retry functionality by monitoring for errors and releasing memory space only when no errors occur during a monitoring period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are written to a FIFO buffer in the memory controller, then the command transmission is simple and straightforward, but the memory access performance deteriorates due to detrimental output order increasing read/write turn-around wait time
Solution Approach 1:
The command reorder device performs preliminary reordering of commands before they are transmitted to the memory. The queue control circuit analyzes incoming commands and rearranges them in advance to optimize the output sequence, reducing read/write turn-around wait time and improving memory access performance.
Solution Approach 2:
The system transitions from a static FIFO buffer to a dynamic reorder queue that can adaptively change command output order based on current memory access patterns. The queue control circuit dynamically adjusts the command sequence to minimize turn-around wait time, making the system flexible rather than rigid.
2Reliability
If an additional retry queue is configured to backup commands for error handling, then command transmission reliability is improved, but the device complexity increases and the retry queue is often left unused
Solution Approach 1:
The retry function is merged with the reorder queue functionality. The same command buffers are used for both reordering commands to optimize memory access and backing up commands for retry. The queue control circuit integrates both functions, eliminating the need for a separate retry queue structure.
Solution Approach 2:
The command buffers serve multiple purposes: they act as reorder buffers to optimize command output order and simultaneously serve as retry buffers to backup commands for error handling. This multi-functional design reduces device complexity while maintaining both reorder and retry capabilities.
3Productivity
If the FIFO buffer maintains input order as output order, then the implementation is simple, but the access performance of the memory deteriorates due to suboptimal command sequencing
Solution Approach 1:
The command reorder device performs preliminary reordering of commands before they are transmitted to the memory. The queue control circuit analyzes incoming commands and rearranges them in advance to optimize the output sequence, reducing read/write turn-around wait time and improving memory access performance.
Solution Approach 2:
The system transitions from a static FIFO buffer to a dynamic reorder queue that can adaptively change command output order based on current memory access patterns. The queue control circuit dynamically adjusts the command sequence to minimize turn-around wait time, making the system flexible rather than rigid.
Data Source
AI summary
A command reorder device with a retry function and an operation method thereof are provided. The command reorder device includes a first switch circuit, multiple command buffers, a second switch circuit, and a queue control circuit. The queue control circuit controls the first switch circuit to push an input command of an input command string to a first command buffer. The queue control circuit controls the second switch circuit to pop out an output command from a second command buffer based on a programmable reorder policy. The queue control circuit checks whether an error notification is received during a monitoring period from when the output command is popped out from the second command buffer. According to the check result, the queue control circuit determines either to pop out the output command from the second command buffer again, or to release the memory space of the second command buffer.