Command Shifter Circuit for Odd-Latency DDR5 Power Saving
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Solution Overview
Problem
The issue of handling odd-numbered latency counts in latency counting of commands using a divided clock signal in semiconductor devices like DDR5 DRAM, which arises due to the increased frequency of clock signals, is addressed.
Innovation Solution
A command shifter circuit with a QED shifter and power save logic that adjusts command widths and delays, allowing for even and odd-numbered clock cycle delays, and a clock control circuit to stop unnecessary clocking, thereby optimizing command processing and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If latency counting of commands is performed using a divided clock signal to secure operation margin at high clock frequencies, then operation reliability is improved, but the system cannot correctly handle odd-numbered latency counts
Solution Approach 1:
The command shifter circuit is divided into multiple shift stages (first shift stage, second shift stage, third shift stage) that can be independently controlled. Each stage can be selectively activated based on whether the latency count is even or odd, allowing the system to handle both cases correctly while maintaining the divided clock signal for operation margin.
Solution Approach 2:
The circuit uses dynamic control signals (first control signal, second control signal, third control signal) that change based on the latency count parity. The control logic dynamically selects which shift stages to activate, enabling the circuit to adapt its behavior for even versus odd latency counts while maintaining reliable operation.
2Adaptability or versatility
If command shifter circuit continuously operates to handle all command patterns, then adaptability to different input patterns is improved, but power consumption increases
Solution Approach 1:
The power save logic selectively activates only the necessary shift stages based on the current command pattern and latency count. Instead of continuously operating all shift stages, the circuit performs partial action by enabling only the required stages (first, second, or third shift stage) for each specific input pattern, thereby reducing power consumption while maintaining full adaptability.
Solution Approach 2:
The power save logic automatically detects the current operational state and selectively enables or disables clocking to shift stages based on actual needs. The circuit self-regulates its power consumption by monitoring command patterns and latency counts, activating clocking only when and where it is necessary for correct operation.
Data Source
AI summary
An example apparatus includes an even global command path configured to drive a first even internal command responsive to a first clock signal, an odd global command path configured to drive a first odd internal command responsive to a second clock signal, and a clock control circuit configured to control whether the first clock signal is provided to at least a portion of the even global command path or not based on a first detection signal activated when the second even internal command keeps an active state during a predetermined period of time and control whether the second clock signal is provided to at least a portion of the odd global command path or not based on the second detection signal activated when the second odd internal command keeps an active state during a predetermined period of time.