Command Signal Delay Adjustment Circuit for DRAM
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Solution Overview
Problem
In semiconductor devices like DRAM, the decoding of external commands by the command decoder introduces a delay in generating internal commands relative to the clock signal, leading to increased charge-discharge current when a constant delayed clock signal is generated, necessitating a solution to synchronize internal commands with the clock signal only during a predetermined period.
Innovation Solution
A control circuit is implemented with a delay line and a walk-back circuit to adjust and synchronize internal commands with the system clock signal, reducing the duration of charge-discharge current by generating a delayed clock signal only when necessary, using a command extension function and latch circuits to ensure synchronization without continuous clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delayed clock signal is constantly generated to synchronize internal commands with the clock signal, then synchronization is achieved, but the amount of charge-discharge current is increased
Solution Approach 1:
The patent applies periodic action by generating the delayed clock signal only during specific periods when command decoding is required, rather than continuously. The delay line generates delayed clock signals in response to external commands during active periods, and stops generating them during idle periods, thereby achieving synchronization when needed while reducing energy consumption during non-critical periods.
2Reliability
If the internal command is latched using a delayed clock signal to compensate for decoding delay, then synchronization is improved, but the device complexity increases
Solution Approach 1:
The patent applies dynamics by making the delayed clock signal generation dynamic rather than static. The delay line is activated only when external commands are received, allowing the system to adaptively generate delayed clock signals based on actual operational needs. This dynamic approach provides precise timing control while avoiding the complexity of continuously active delay circuits.
Data Source
AI summary
An example apparatus includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.