Command Splitter Circuit for Parallel Tile Data Transfer
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Solution Overview
Problem
Current data processing circuits face inefficiencies when performing block level transfers (BLT) with overlapping source and destination blocks, leading to wasted hardware resources and low execution efficiency due to the inability to process tiles in parallel, which results in potential data corruption and failure to utilize high bandwidth.
Innovation Solution
A data transferring apparatus and method that utilizes a command splitter circuit to split BLT commands into batches and execute them in parallel using multiple tile processing circuits, ensuring that each batch is completed before issuing the next, thereby preventing data corruption and maximizing hardware resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed in parallel using multiple tile processing units, then execution efficiency is improved, but data corruption occurs when source and destination blocks overlap
Solution Approach 1:
The patent segments the data transfer process into distinct batches, where each batch contains tile transfer tasks that do not overlap in address space. The command splitter divides the overall transfer operation into multiple batches, processing them sequentially to prevent data corruption while maintaining parallel execution within each batch.
Solution Approach 2:
The patent performs preliminary analysis of source and destination block addresses to identify overlapping regions before executing data transfer. The command splitter pre-processes transfer commands to determine safe batching strategies, ensuring that parallel execution will not cause write-after-read conflicts.
2Reliability
If only one tile processing unit is used to prevent data corruption, then data correctness is maintained, but hardware resources are wasted and execution efficiency decreases
Solution Approach 1:
The patent dynamically adjusts the degree of parallelism based on the overlap characteristics of source and destination blocks. When blocks overlap, the command splitter reduces parallelism by processing batches sequentially. When blocks do not overlap, full parallelism is utilized, maximizing hardware resource usage while maintaining data correctness.
Solution Approach 2:
The system changes the batching parameter dynamically based on address overlap detection. The command splitter adjusts batch composition and processing order to optimize the balance between parallel execution and data correctness, transforming the static single-threaded approach into a dynamic multi-threaded system.
3Reliability
If sequential tile transfer is performed to avoid write after read conflicts, then data correctness is ensured, but hardware resources remain idle and bandwidth utilization is low
Solution Approach 1:
The patent ensures continuous utilization of hardware resources by organizing tile transfers into batches that can be executed in parallel without causing data corruption. The command splitter continuously feeds batches to available processing units, eliminating idle time while maintaining data correctness through careful batch ordering and address space management.
Data Source
AI summary
A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.