Command Timing Control Circuit for DRAM Read Modify Write
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Solution Overview
Problem
The timing of the read command signal during a read modify write (RMW) operation in DRAM cannot meet the required timing conditions due to variations in frequency and write preamble signals, leading to insufficient time for intermediate operations like ECC.
Innovation Solution
A command timing control circuit is introduced, comprising a decoding circuit and a shift circuit. The decoding circuit processes frequency indication and write preamble signals to generate a control signal, which indicates the duration for shifting the RMW command signal. The shift circuit then adjusts the RMW command signal accordingly to meet the preset timing condition between the target command signal and the write enable signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read command signal is generated without timing adjustment, then the RMW operation can be initiated quickly, but the time interval between the read command and write enable signal does not meet the preset timing condition, causing insufficient time for intermediate operations like ECC
Solution Approach 1:
The patent implements dynamic timing adjustment by using a shift circuit that can vary the timing of the read modify write command signal based on decoded control signals. The shift amount is dynamically determined by decoding the frequency indication signal and write preamble signal, allowing the system to adapt the timing to meet preset conditions while maintaining operational efficiency.
Solution Approach 2:
The patent changes the timing parameter of the read modify write command signal by shifting it in time based on decoded control information. The shift amount is determined by decoding the frequency indication signal and write preamble signal, which allows the system to adjust the time interval between commands to satisfy preset timing conditions for reliable intermediate operations.
2Adaptability or versatility
If a fixed shift duration is applied to the RMW command signal, then the timing can be simplified, but it cannot adapt to different frequency values and write preambles, leading to timing condition violations under varying operating conditions
Solution Approach 1:
The patent introduces a decoding circuit as an intermediary that processes the frequency indication signal and write preamble signal to generate appropriate control signals for the shift circuit. This intermediary layer enables the system to adapt to different operating conditions by translating varied input signals into the correct timing adjustments without requiring complex direct control logic.
Solution Approach 2:
The patent divides the timing control function into two separate modules: a decoding circuit that processes input signals and generates control information, and a shift circuit that applies the timing adjustment based on the control signals. This segmentation allows each module to perform its function efficiently while maintaining adaptability to different frequency values and write preambles.
Data Source
AI summary
A command timing control circuit includes a decoding circuit and a shift circuit, where the decoding circuit is configured to perform decoding processing according to a frequency indication signal and a write preamble signal, and generate a control signal, the control signal indicating a first duration for shifting a read modify write command signal; and the shift circuit is configured to shift the read modify write command signal by the first duration according to the control signal, and generate a target command signal, such that a time interval between the target command signal and a write enable signal meets a preset timing condition.