Internal Command Timing Circuit With Shared Delay and Phase Control
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently managing latency and synchronization of internal commands and clocks, leading to increased power and area consumption due to the need for multiple delay circuits.
Innovation Solution
A semiconductor device design that generates synthesized commands and internal commands using a single delay circuit, with clock phases controlled by a phase control signal, allowing for flexible delay adjustments and reduced power and area usage by merging delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple delay circuits are used to manage latency and synchronization of internal commands and clocks, then the reliability of data input/output operations is improved, but the power consumption and area consumption increase
Solution Approach 1:
The patent merges multiple delay circuits into a single shared delay circuit that serves multiple internal commands and clocks. This consolidation maintains the necessary latency and synchronization control while reducing the total number of delay circuits from multiple to one, thereby decreasing power consumption and area usage without compromising the reliability of data input/output operations.
2Reliability
If multiple delay circuits are used to manage latency and synchronization of internal commands and clocks, then the reliability of data input/output operations is improved, but the area consumption increases
Solution Approach 1:
The patent merges multiple delay circuits into a single shared delay circuit that serves multiple internal commands and clocks. This consolidation maintains the necessary latency and synchronization control while reducing the total number of delay circuits from multiple to one, thereby decreasing the area consumption without compromising the reliability of data input/output operations.
3Use of energy by moving object
If a single delay circuit is used to generate synthesized commands and internal commands, then the power consumption and area usage are reduced, but the delay period increases
Solution Approach 1:
The patent implements a phase control signal that dynamically adjusts the phase of the clock signal to the delayed command, allowing the system to optimize the delay period in real-time. This dynamic adjustment compensates for the increased delay period caused by using a single delay circuit, ensuring that the overall system performance is maintained while benefiting from reduced power consumption and area usage.
4Area of stationary object
If a single delay circuit is used to generate synthesized commands and internal commands, then the area usage is reduced, but the delay period increases
Solution Approach 1:
The patent implements a phase control signal that dynamically adjusts the phase of the clock signal to the delayed command, allowing the system to optimize the delay period in real-time. This dynamic adjustment compensates for the increased delay period caused by using a single delay circuit, ensuring that the overall system performance is maintained while benefiting from reduced area usage.
Data Source
AI summary
A semiconductor device includes an internal command generation circuit configured to generate a synthesized command from a command which is inputted in synchronization with any one of a first internal clock and a third internal clock generated by dividing a frequency of a clock, and configured to generate a first internal command and a second internal command by delaying the synthesized command depending on a detected input time of the command. The semiconductor device also includes a data transmission circuit configured to generate transmission data from data in synchronization with any one of the first internal command and the second internal command.