Commodity FPGA Logic Drive With Non-Volatile LUT Memory
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Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips for advanced semiconductor applications, due to larger chip size, higher power consumption, and increased Non-Recurring Engineering (NRE) costs, hinder innovation and adoption of advanced technology nodes.
Innovation Solution
A standardized commodity logic drive utilizing multiple standardized commodity FPGA IC chips for various applications, reducing NRE costs by allowing developers to field-program these chips for computing and processing functions, similar to how DRAM or flash memory chips are used, and providing a public innovation platform for implementing advanced algorithms and applications at lower costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for advanced semiconductor applications, then adaptability and ease of operation are improved, but chip size, power consumption, and fabrication cost increase
Solution Approach 1:
The patent segments the FPGA chip structure into multiple logic blocks and programmable interconnection resources. Each logic block can be independently configured and activated, allowing the chip to be divided into functional units that can be selectively used based on application requirements, thereby reducing the effective area needed for specific implementations
Solution Approach 2:
The patent implements universal logic blocks that can be programmed to perform multiple different logic functions. These logic blocks contain configurable elements such as look-up tables (LUTs) and flip-flops that can be programmed through configuration memory to implement various digital circuits, allowing a single chip design to serve multiple applications without requiring different physical chip areas
2Adaptability or versatility
If FPGA IC chips are used for advanced semiconductor applications, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management through programmable logic blocks that can be selectively enabled or disabled based on configuration. The configuration memory allows different logic blocks to be activated only when needed for specific applications, reducing overall power consumption compared to having all logic blocks permanently active. The programmable interconnection resources also allow dynamic routing to minimize signal path length and reduce switching power
Solution Approach 2:
The patent changes the operational parameters of the FPGA chip through configuration programming. By loading different configuration data into the configuration memory, the chip can be reprogrammed to optimize power consumption for different applications. The logic blocks can be configured to use different operating modes, voltage levels, and timing parameters to minimize power usage while maintaining adaptability
3Ease of manufacture
If ASIC or COT IC chips are used instead of FPGA, then fabrication cost and power consumption are reduced, but Non-Recurring Engineering costs increase significantly
Solution Approach 1:
The patent uses configuration memory to store programmable data that defines the logic function of each logic block. This configuration data acts as a software copy that can be loaded and reloaded without changing the physical chip structure. The configuration memory contains bitstreams that program the logic blocks and interconnection resources, allowing the same physical chip to be replicated for different applications through software programming rather than requiring expensive custom mask sets for each application
Solution Approach 2:
The patent performs all customization and configuration work during the programming phase rather than during fabrication. The configuration memory is pre-designed with the capability to store various logic configurations, and the specific application logic is loaded into this memory through standard programming interfaces. This preliminary preparation of the configurable structure eliminates the need for expensive post-fabrication customization processes such as mask re-spinning required for ASICs
4Ease of operation
If FPGA IC chips are used, then ease of operation and adaptability are improved, but fabrication yield decreases
Solution Approach 1:
The patent designs a universal FPGA chip architecture that uses standardized logic blocks and interconnection resources that can be programmed for different applications. This universal design approach allows the same physical chip structure to serve multiple functions, reducing the complexity of manufacturing different variants. The configuration memory and programmable resources are designed once and can be manufactured with high yield using standard semiconductor fabrication processes, unlike custom ASIC designs that require separate fabrication runs for each application
Data Source
AI summary
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.