Common Bit Line Structure for Nonvolatile Memory Devices
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Solution Overview
Problem
Conventional nonvolatile memory devices require a large number of bit lines, leading to increased parasitic capacitance and reduced operating speeds due to close bit line proximity, which hinders the integration and data processing capabilities of semiconductor memory devices.
Innovation Solution
The implementation of a nonvolatile memory device structure where multiple memory strings share a common bit line, with first and second selection transistors having different driving voltages and a common bit line connecting the ends of each memory string, allowing for reduced bit line count and increased pitch between bit line contacts, thereby reducing parasitic capacitance and enhancing operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple bit lines are used to connect each memory string individually, then memory access reliability is improved, but parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The patent combines multiple bit lines into a shared common bit line that serves multiple memory strings simultaneously. This merging approach reduces the total number of bit lines from one per memory string to a shared resource, thereby reducing parasitic capacitance and improving operating speed while maintaining reliable memory access through the selection transistor mechanism
Solution Approach 2:
The patent introduces selection transistors as intermediary components between the shared bit line and individual memory strings. These transistors act as mediators that enable reliable selective access to specific memory strings while sharing the common bit line, thus maintaining access reliability without requiring dedicated bit lines for each string
2Area of stationary object
If bit lines are placed close together to increase integration density, then device area is reduced, but parasitic capacitance between bit lines increases
Solution Approach 1:
By merging multiple bit lines into a single shared common bit line, the patent eliminates the need for closely spaced parallel bit lines. This consolidation reduces the total bit line count and the associated parasitic capacitance between adjacent bit lines, while still providing access to multiple memory strings through the selection transistor control mechanism
3Speed
If the number of bit lines is reduced to decrease parasitic capacitance, then operating speed is improved, but memory string accessibility may be compromised
Solution Approach 1:
The selection transistors serve as intermediary control elements that enable a single shared bit line to access multiple memory strings selectively. By controlling the selection transistors with appropriate word lines, the system maintains full memory string accessibility while using fewer bit lines, thus improving operating speed without sacrificing versatility
Solution Approach 2:
The patent employs dynamic control of selection transistors through word line voltages to enable selective access to different memory strings via the shared bit line. This dynamic switching mechanism allows the system to adaptively route the shared bit line to different memory strings as needed, maintaining accessibility while reducing the static number of bit lines required
Data Source
AI summary
Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings.