Common Body Bias Region for Compact NMOS Bias Routing
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Solution Overview
Problem
As the integration of semiconductor devices increases, the available area for forming semiconductor elements decreases, leading to challenges in efficiently providing bias voltage to transistors without increasing wiring complexity and device area.
Innovation Solution
A semiconductor device with a common body bias region that contacts both the P-well region and the substrate, allowing both NMOS transistors to share a single body bias terminal, reducing the overall area and wiring complexity by providing a bias voltage simultaneously to both transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate body bias regions are provided for each NMOS transistor, then each transistor can be independently biased, but the device area and wiring complexity increase
Solution Approach 1:
The patent combines separate body bias regions for multiple NMOS transistors into a single common body bias region. This common region is formed by extending a body bias contact plug through the substrate to contact both the P-well region (for first NMOS) and the substrate (for second NMOS), eliminating the need for separate bias regions and reducing overall device area.
Solution Approach 2:
The common body bias region serves multiple functions simultaneously: it provides body bias to both the first NMOS transistor (through contact with P-well) and the second NMOS transistor (through contact with substrate). This multi-functional design allows a single structure to replace what would traditionally require separate dedicated structures for each transistor.
2Reliability
If separate body bias regions are provided for each NMOS transistor, then each transistor can be independently biased, but the wiring complexity increases
Solution Approach 1:
The patent merges multiple bias voltage paths into a single common body bias region. By forming one extended contact structure that contacts both the P-well and substrate, the patent eliminates the need for separate wiring paths to different bias regions, thereby reducing wiring complexity while maintaining independent bias capability.
Solution Approach 2:
The common body bias region acts as an intermediary structure that mediates between the bias voltage source and multiple transistors. Instead of requiring separate wiring from the bias source to each transistor's body region, the common body bias region receives the bias voltage once and distributes it to multiple transistors through its extended contact structure.
3Area of stationary object
If a common body bias region is shared by multiple NMOS transistors, then the device area is reduced, but electrical interference may occur
Solution Approach 1:
While using a common body bias region, the patent maintains electrical separation between different transistor bodies through the substrate structure. The common contact plug contacts the P-well region at one depth and the substrate at another, creating electrically isolated bias paths for different transistor types while sharing the same physical contact structure.
Data Source
AI summary
A semiconductor device includes a substrate, a P-well region, a first N-type metal oxide semiconductor (NMOS) transistor provided in the P-well region, a second NMOS transistor provided on the substrate, and a common body bias region provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.