Common-Centroid IC Layout Generation with Parasitic-Aware Cost Evaluation

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Solution Overview

Problem

Existing IC layout generation methods fail to effectively reduce area, wirelength, and routing-induced parasitics while maintaining capacitance ratio accuracy, as they neglect the impact of induced parasitics post-routing.

Innovation Solution

A method involving acquiring a netlist, determining a unit element array with an aspect ratio closest to 1, generating common-centroid placements, applying global routing assignment, evaluating costs for matching quality and parasitics, and selecting optimal placements for detailed routing to minimize wirelength and parasitics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If common-centroid placement is applied to improve matching quality, then capacitance ratio accuracy is improved, but routing-induced parasitics increase due to wire routing

Engineering Contradiction:
Improvecapacitance ratio accuracyVSAvoidrouting-induced parasitics
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by performing cost evaluation that includes parasitic estimation before final routing decisions are made. The method estimates routing-induced parasitics during the placement phase and uses this information to guide placement optimization, rather than addressing parasitics after routing is complete.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using cost evaluation results that combine matching quality metrics with parasitic estimates. This feedback loop allows the placement algorithm to iteratively adjust common-centroid placements to achieve optimal balance between matching quality and parasitic minimization.

Inventive Principle:
Principle #23Feedback

2Area of stationary object

If traditional layout methods are used, then area and wirelength are not optimized, but matching quality and parasitic control are improved

Engineering Contradiction:
Improvelayout areaVSAvoidmatching quality
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent applies parameter changes by optimizing the unit element array aspect ratio to be closest to 1, which fundamentally changes the geometric parameters of the layout. This aspect ratio optimization enables both compact area utilization and maintained matching quality, resolving the contradiction between area efficiency and matching precision.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If routing is performed after common-centroid placement, then connectivity is achieved, but induced parasitics increase and matching quality degrades

Engineering Contradiction:
Improverouting connectivityVSAvoidinduced parasitics
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent performs preliminary estimation of routing-induced parasitics before final routing is executed. By evaluating parasitic costs during the placement phase, the method guides placement decisions to minimize future parasitic impacts, addressing the harmful effects before they fully manifest.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent skips the traditional sequential approach by integrating parasitic evaluation into the placement phase itself, rather than treating routing and parasitic analysis as separate subsequent steps. This integration allows simultaneous optimization of connectivity and parasitic minimization.

Inventive Principle:
Principle #21Skipping (Rushing through)

4Measurement precision

If multiple common-centroid placements are generated, then optimization options increase, but evaluation complexity and computation time increase

Engineering Contradiction:
Improvematching quality optimizationVSAvoidevaluation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing an automated cost evaluation system that simultaneously assesses multiple placements across multiple nets. The method uses efficient algorithms to compute matching quality and parasitic estimates for multiple candidates, allowing the system to self-evaluate and select optimal placements without excessive computational burden.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8751995B1Method of common-centroid IC layout generation
Publication Date: 2014.06.10 NATIONAL CHUNG CHENG UNIV
  • US8751995B1 patent drawing
  • US8751995B1 patent drawing
  • US8751995B1 patent drawing

AI summary

A method of common-centroid IC layout generation includes the following steps of acquiring a netlist of one circuit-element set; summing up the numbers of the unit element of all elements of the circuit-element set to get the total number of the unit elements and then determine the unit element array, the aspect ratio of which is closest to 1, via a combination operation; generating multiple common-centroid placements according to the unit element array and applying global routing assignment to each of the common-centroid placements; proceeding with cost evaluation in such a way that a cost calculation is applied to each of the common-centroid placements to get a corresponsive value; and comparing all of the common-centroid placements according to the values got from the cost evaluation and selecting the common-centroid placement corresponding to one of the values according to a predetermined condition for detailed routing.