Common Centroid Reference Voltage Circuit for Stress-Induced Variation
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Solution Overview
Problem
Semiconductor devices with reference voltage circuits experience characteristic fluctuations due to stress from resin encapsulation, leading to product variation.
Innovation Solution
The transistors in the reference voltage circuit are arranged in a common centroid configuration, where depletion and enhancement type transistors are connected in series or parallel, ensuring that both types of transistors experience the same influence from stress, thereby minimizing characteristic deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are arranged in a conventional layout, then the reference voltage circuit can be implemented with simple structure, but the transistors experience different stress influences causing characteristic fluctuations
Solution Approach 1:
The patent applies asymmetry principle by intentionally creating a symmetric common centroid arrangement of transistors to counteract the asymmetric stress distribution from resin encapsulation. By positioning transistors T1-T4 in a symmetric pattern around a central point, the circuit ensures that stress effects are distributed equally across all transistors, preventing characteristic deviations that would occur with conventional asymmetric layouts.
Solution Approach 2:
The common centroid arrangement creates an equipotential configuration where all transistors experience equivalent stress conditions. This symmetric positioning ensures that each transistor is subjected to the same mechanical stress from resin encapsulation, making their electrical characteristics consistent and eliminating the potential differences that arise from unequal stress distribution in conventional layouts.
2Manufacturing precision
If transistors are arranged to experience the same stress influence, then characteristic fluctuations are minimized, but the layout requires more careful design and occupies more area
Solution Approach 1:
The reference voltage circuit is segmented into multiple transistor units (T1-T4) that are individually positioned and then collectively arranged in a common centroid configuration. This segmentation allows each transistor to be optimized for its specific function while the overall symmetric arrangement ensures uniform stress distribution, achieving both manufacturing precision and reasonable area utilization.
Solution Approach 2:
The patent transitions from a conventional linear or compact transistor arrangement to a two-dimensional common centroid layout. By distributing transistors in a spatial pattern around a central point rather than arranging them in a simple sequence, the design achieves uniform stress exposure across all transistors while maintaining area efficiency through optimized spatial positioning.
Data Source
AI summary
There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.